as6c2008a Alliance Memory, Inc, as6c2008a Datasheet - Page 7

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as6c2008a

Manufacturer Part Number
as6c2008a
Description
512k X 8 Bit Low Po 256k X 8 Bit Low Power Cmos Sram
Manufacturer
Alliance Memory, Inc
Datasheet
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, t
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
6.t
placed on the bus.
impedance state.
OW
and t
WHZ
are specified with C
(WE# Controlled) (1,2,3,5,6)
(CE# and CE2 Controlled) (1,2,5,6)
L
= 5pF. Transition is measured ±500mV from steady state.
WP
must be greater than t
WHZ
+ t
DW
to allow the drivers to turn off and data to be

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