as6c6264a Alliance Memory, Inc, as6c6264a Datasheet

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as6c6264a

Manufacturer Part Number
as6c6264a
Description
? 8k?x?8?bit?low?power?cmos?sram
Manufacturer
Alliance Memory, Inc
Datasheet
 
F
P
 
MARCH 2009 
MARCH/2009 
EATURES
IN 
8192 x 8 bit static CMOS RAM
70 ns Access Times
Common data inputs and
outputs
Three-state outputs
Typ. operating supply current
Standby current:
Data retention current at 2 V:
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges:
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Packages: PDIP28 (600 mil)
C
ONFIGURATION
o
o
o
o
o
 
70 ns: 10 mA
< 2 μA at T
< 1 μA at T
0 to 70 °C
-40 to 85 °C
SOP28 (330 mil)
 
a
a
≤ 70 °C
≤ 70 °C
8K X 8 BIT LOW POWER CMOS SRAM
D
The AS6C6264A is a static RAM
manufactured using a CMOS
process technology with the
following operating modes:
The memory array is based on a 6-
transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The address
and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word read will
be available at the outputs DQ0 -
DQ7. After the address change, the
data outputs go High-Z until the new
read information is available. The
data outputs have no preferred
state. If the memory is driven by
CMOS levels in the active state, and
if there is no change of the address,
ESCRIPTION
- Read - Standby
- Write - Data Retention
ALLIANCE MEMORY
 
P
IN 
 
D
ESCRIPTION
 
data input and control signals W or
G, the operating current (at IO = 0
mA) drops to the value of the
operating current in the Standby
mode. The Read cycle is finished by
the falling edge of E2 or W, or by
the rising edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so that
no pull-up/pull-down resistors are
required. This gate circuit allows to
achieve low power standby
requirements by activation with TTL-
levels too.
If the circuit is inactivated by E2 = L,
the standby current
PAGE 1 of 10
AS6C6264A 

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as6c6264a Summary of contents

Page 1

... ONFIGURATION   MARCH/2009    8K X 8 BIT LOW POWER CMOS SRAM D   ESCRIPTION The AS6C6264A is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based transistor cell. ...

Page 2

... MARCH 2009      LOCK  IAGRAM T T   RUTH  ABLE   MARCH/2009    8K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C6264A  PAGE 2 of 10 ...

Page 3

... Maximum voltage Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.   MARCH/2009    8K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C6264A  PAGE 3 of 10 ...

Page 4

... MARCH 2009      MARCH/2009    8K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C6264A  PAGE 4 of 10 ...

Page 5

... MARCH 2009      MARCH/2009    8K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C6264A  PAGE 5 of 10 ...

Page 6

... MARCH 2009    EST  ONFIGURATION FOR  UNCTIONAL    MARCH/2009    8K X 8 BIT LOW POWER CMOS SRAM C   HECK ALLIANCE MEMORY AS6C6264A  PAGE 6 of 10 ...

Page 7

... MARCH 2009      MARCH/2009    8K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C6264A  PAGE 7 of 10 ...

Page 8

... The information describes the type of component and shall not be considered as assured characteristic. Terms of  delivery and rights to change design reserved.    MARCH/2009    8K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C6264A  PAGE 8 of 10 ...

Page 9

... P-DIP -70 X Temperature Range: Package Option Commercial Access P=28pin 600mil PDIP Time S=28pin 330mil SOP I = Industrial ALLIANCE MEMORY AS6C6264A  Speed Operating Temp ns Commercial – Industrial ~ - Commercial – Industrial ~ - ...

Page 10

... MARCH/2009    8K X 8 BIT LOW POWER CMOS SRAM ALLIANCE MEMORY AS6C6264A  Copyright © Alliance Memory   All Rights Reserved PAGE 10 of 10 ...

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