as7c4096a Alliance Memory, Inc, as7c4096a Datasheet - Page 6

• Manufacturer Part Number: as7c4096a
• Description: 5.0v 512k ? 8 Cmos Sram
• Manufacturer: Alliance Memory, Inc

Write waveform 2 (CE controlled)
AC test conditions
Notes
1
2
3
4
5
6
7
8
9
10 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
V
Address
- Output load: see Figure B.
- Input pulse level: GND to V
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
CC
2/21/06, v 1.2
During V
For test conditions, see AC Test Conditions.
t
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CE and OE are LOW for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
CLZ
D
WE
- 0.5V
CE
IN
GND
and t
CC
CHZ
power-up, a pull-up resistor to V
10%
are specified with C
Figure A: Input pulse
90%
2 ns
L
t
CC
90%
AS
= 5pF as in Figure B. Transition is measured ±500 mV from steady-state voltage.
10%
- 0.5V. See Figures A and B.
CC
on CE is required to meet I
9
Alliance Semiconductor
t
AW
t
WP
D
t
CW
Figure B: 5.0V Output load
OUT
t
WC
255Ω
t
DW
Data valid
SB
specification.
+5.0V
480Ω
C
GND
®
10
t
t
WR
AH
t
DH
D
OUT
Thevenin equivalent:
168Ω
+1.728V
AS7C4096A
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