as7c1025b Alliance Memory, Inc, as7c1025b Datasheet - Page 6

• Manufacturer Part Number: as7c1025b
• Description: 5v 128k X 8 Cmos Sram Center Power And Ground
• Manufacturer: Alliance Memory, Inc

3/26/04, v. 1.3
Write waveform 2 (CE controlled)
AC test conditions
Notes
1
2
3
4
5
6
7
8
9
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
Address
D
During V
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A and B.
t
This parameter is guaranteed, but not 100% tested.
WE is high for read cycle.
CE and OE are low for read cycle.
Address is valid prior to or coincident with CE transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CLZ
– Output load: see Figure B.
– Input pulse level: GND to 3.5 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
OUT
WE
D
CE
+3.5 V
IN
and t
GND
CC
CHZ
power-up, a pull-up resistor to V
10%
are specified with CL = 5 pF, as in Figure B. Transition is measured ±500 mV from steady-state voltage.
Figure A: Input pulse
90%
2 ns
t
AS
90%
10%
CC
Alliance Memory Inc.
on CE is required to meet I
10,11
t
WZ
t
AW
Figure B: 5 V Output load
D
OUT
t
255 Ω
CW
t
t
WP
WC
t
Data valid
DW
SB
+5 V
480 Ω
C
GND
®
specification.
13
t
t
WR
AH
t
DH
D
OUT
Thevenin equivalent:
168 Ω
+1.728 V
P. 6 of 9
AS7C1025B