as7c25512ft3236a ETC-unknow, as7c25512ft3236a Datasheet - Page 4

• Manufacturer Part Number: as7c25512ft3236a
• Manufacturer: ETC-unknow

Functional description
The AS7C25512FT32A/36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized
expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The
burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data
accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is
ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for
the next access of the burst when ADV is sampled LOW and both address strobes are HIGH. Burst mode is selectable with the LBO input.
With LBO unconnected or driven HIGH, burst operations use an interleaved count sequence. With LBO driven LOW, the device uses a linear
count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP LOW, but it is sampled on all subsequent clock edges. Output buffers are disabled
when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled LOW. Address is
incremented internally to the next burst address if BWn and ADV are sampled LOW.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are
as follows:
The AS7C25512FT32A/36A family operates from a core 2.5V power supply. These devices are available in a 100-pin TQFP package.
TQFP capacitance
* Guaranteed not tested
TQFP thermal resistance
1 This parameter is sampled
as 524,288 words x 32/36.
Fast cycle times of 8.5/10/12 ns with clock access times (t
Input capacitance
I/O capacitance
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to top of case)
12/23/04, v. 1.2
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
• Master chip enable CE0 blocks ADSP, but not ADSC.
Parameter
Description
1
1
Symbol
C
C
I/O
IN
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
*
*
Test conditions
Alliance Semiconductor
V
V
OUT
Conditions
IN
= 0V
= 0V
CD
) of 7.5/8.5/10.0 ns. Three chip enable (CE) inputs permit easy memory
®
Min
-
-
1–layer
4–layer
Max
5
7
Symbol
θ
θ
θ
Unit
JA
JA
JC
pF
pF
AS7C25512FT32A
AS7C25512FT36A
Typical
40
22
8
4 of 19
Units
°C/W
°C/W
°C/W