as7c33512ntd32a Alliance Memory, Inc, as7c33512ntd32a Datasheet
as7c33512ntd32a
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as7c33512ntd32a Summary of contents
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... D Address register Burst logic CLK D Write delay addr. registers CLK Control logic CLK 32/36 32/36 Data D Q Input Register CLK OE -166 6 166 3.4 300 90 60 Alliance Semiconductor AS7C33512NTD32A AS7C33512NTD36A TM DDQ Q 19 CLK 512K x 32/36 SRAM Array 32/36 32/36 32/36 CLK Output Register OE 32/36 DQ[a,b,c,d] -133 Units 7.5 ns 133 MHz 3.8 ns 275 mA 80 ...
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... Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD- Alliance Semiconductor AS7C33512NTD32A/36A 3 Speed 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/ ...
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... DQd4 25 DQd5 V 26 SSQ V 27 DDQ 28 DQd6 29 DQd7 30 NC/DQPd Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration. 4/21/05, v 2.8 ® TQFP 14 x 20mm Alliance Semiconductor AS7C33512NTD32A/36A 80 DQPb/NC 79 DQb7 78 DQb6 77 V DDQ 76 V SSQ 75 DQb5 74 DQb4 73 DQb3 72 ...
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... Functional Description The AS7C33512NTD32A/36A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory (SRAM) organized as 524,288 words × bits and incorporates a LATE LATE Write. This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD write operation that improves bandwidth over pipelined burst devices normal pipelined burst device, the write data, command, and address are all applied to the device on the same clock edge ...
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... DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. PUS 4/21/05, v 2.8 ® Description or left floating, device follows interleaved Burst order. When DD is guaranteed after the time t is met. After entering SNOOZE MODE, all inputs except ZZ SB2 ZZI Alliance Semiconductor AS7C33512NTD32A/36A . The duration of SB2 ...
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... External NOP/WRITE ABORT (Begin Burst) High Next Current enables WRITEs to byte “b” (DQb pins); Alliance Semiconductor AS7C33512NTD32A/36A Linear burst order (LBO = ...
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... Min Nominal V 3.135 3 3.135 3.3 DDQ Vss 0 0 Symbol Min Nominal V 3.135 3 2.375 2.5 DDQ Vss 0 0 Alliance Semiconductor AS7C33512NTD32A/36A Burst Dsel Burst Burst Min Max Unit –0.5 +4.6 –0 0.5 DD –0 0.5 DDQ – 1.8 – –65 +150 o –65 +135 Max Unit 3 ...
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... Deselected < Max IL Deselected < 0.2V, ≤ 0.2V or ≥ V all V – 0. ≥ V Deselected Max DD ≤ ≥ V all Alliance Semiconductor AS7C33512NTD32A/36A Min Max Unit -2 2 µA DD < µA DDQ +0.3 DDQ -0.3** 0 ...
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... 0.5 CSH t 1.5 CENS t 0.5 CENH t 1.5 ADVS t 0.5 ADVH Conditions Symbol ZZ > SB2 t PDS t PUS t ZZI t RZZI Alliance Semiconductor AS7C33512NTD32A/36A -133 1 Min Max Unit Notes – 133 MHz – 7.5 – ns – 3.8 ns – 3.8 ns – 0 – ns 2,3,4 – 1.5 – – 0 – ns 2,3,4 – 3.8 ns 2,3,4 – ...
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... Falling input HZOE OE Q(A1) Q(A2) Q(A2Y‘01) Read Continue Continue Continue Q(A2) Read Read Q(A2Y‘10) Q(A2Y‘01) Q(A2Y‘11) Alliance Semiconductor AS7C33512NTD32A/36A Undefined t CYC A3 Q(A2Y‘10) Q(A3) Q(A2Y‘11) Continue Inhibit Read Read Read Clock Q(A3) Q(A3Y‘01 HLZC ...
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... HZOE Dout Q(n-2) Q(n-1) Write DSEL D(A1) 4/21/05, v 2.8 ® D(A1) D(A2) D(A2Y‘01) Write Continue Continue Continue D(A2) Write Write Write D(A2Y‘10) D(A2Y‘01) D(A2Y‘11) Alliance Semiconductor AS7C33512NTD32A/36A t CYC D(A3) D(A2Y‘10) D(A2Y‘11) Continue Inhibit Write Write Clock D(A3) D(A3Y‘01 ...
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... Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don’t care. 4/21/05, v 2.8 ® LZC OH D(A1) D(A2) Q(A3) D(A2Ý01) Burst Burst Read Read Write Read Q(A3) Q(A4) D(A2Ý01) Q(A4Ý01) Alliance Semiconductor AS7C33512NTD32A/36A t CYC HZC D(A5) Q(A6) Q(A4) Q(A4Ý01) t HZOE t LZOE Write Read Write D(A5) Q(A6) D(A7 DSEL ...
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... Address A1 D/Q Command Read Burst Q(A1) Q(A1Ý01) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low low. 4/21/05, v 2.8 ® A2 Q(A1Ý01) Q(A1) Q(A1Ý10) STALL Burst DSEL Burst Q(A1Ý10) DSEL Alliance Semiconductor AS7C33512NTD32A/36A A3 D(A2) Burst Write Write Burst NOP NOP D(A2) D(A2Ý10) D(A2Ý01) D(A3 ...
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... Timing waveform of snooze mode CLK ZZ setup cycle ZZ t ZZI I supply I SB2 All inputs Deselect or Read Only (except ZZ) Dout 4/21/05, v 2.8 ® t PUS ZZ recovery cycle t RZZI Deselect or Read Only High-Z Alliance Semiconductor AS7C33512NTD32A/36A Normal operation Cycle ...
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... L for 3.3V I/ DDQ for 2.5V I/O Figure B: Output load (A) at any given temperature and voltage. LZC IL Alliance Semiconductor AS7C33512NTD32A/36A Thevenin equivalent: +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O 319Ω/1667Ω D OUT 5 pF* 353Ω/1538Ω GND *including scope and jig capacitance Figure C: Output load(B) ...
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... Package dimensions 100-pin quad flat pack (TQFP) TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 1.00 nominal α 0° 7° Dimensions in millimeters 4/21/05, v 2.8 ® Alliance Semiconductor AS7C33512NTD32A/36A b e α ...
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... Ordering information Package & Width TQFP x32 TQFP x36 Notes: Add suffix ‘N’ to the above part number for Lead Free Parts (Ex. AS7C33512NTD32A-166TQCN) Part numbering guide AS7C 33 512 Alliance Semiconductor SRAM prefix 2. Operating voltage 3.3V 3. Organization: 512 = 512k 4. NTD™ Turn-Around Delay, Pipelined mode. ...
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... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. AS7C33512NTD32A/36A ® Copyright © Alliance Semiconductor All Rights Reserved Part Number:AS7C33512NTD32A/36A Document Version: v 2.8 ...