as7c3364pfs32a Alliance Memory, Inc, as7c3364pfs32a Datasheet

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as7c3364pfs32a

Manufacturer Part Number
as7c3364pfs32a
Description
3.3v 32/36 Pipeline Burst Synchronous Sram
Manufacturer
Alliance Memory, Inc
Datasheet
Logic block diagram
Features
• Organization: 65,536 words × 32 or 36 bits
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns
• Fast OE access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” mode
• Single-cycle deselect
• Pentium®
A[15:0]
Selection guide
*
ment are the property of their respective owners.
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
Pentium
ADSC
January 2001
Preliminary Information
ADSP
GWE
BWE
CLK
BW
BW
BW
ADV
BW
CE0
CE1
CE2
OE
2/1/01; V.0.9
ZZ
d
c
b
a
®
is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this docu-
Power
down
*
compatible architecture and timing
16
D
CE
CLK
D
CLK
D
CLK
D
CLK
D
CLK
D
CE
CLK
D
CLK
CLK
CE
CLR
Byte write
Byte write
Byte write
Byte write
registers
registers
registers
registers
register
Address
register
Enable
register
delay
DQ
DQ
DQ
Enable
DQ
d
c
b
a
Q
Burst logic
Q
Q
Q
Q
Q
Q
LBO
16
3.3V 64K X 32/36 pipeline burst synchronous SRAM
Q0
Q1
AS7C3364PFS32A
14
–166
166
475
130
3.5
16
30
CLK
6
Alliance Semiconductor
OE
36/32
registers
Output
4
FT
64K × 32/36
Memory
DATA [35:0]
DATA [31:0]
array
36/32
CLK
registers
Input
AS7C3364PFS32A
–150
150
450
110
6.7
3.8
30
• Asynchronous output enable control
• Economical 100-pin TQFP package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate V
• 30 mW typical standby power in power down mode
Pin arrangement
DQP
DQP
®
d
c
V
V
V
V
/NC
V
V
V
V
/NC
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DDQ
DDQ
V
DDQ
DDQ
NC
V
SSQ
SSQ
SSQ
SSQ
AS7C3364PFS32A
FT
DD
SS
d
d
d
d
d
d
d
d
c
c
c
c
c
c
c
c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Note: Pins 1,30,51,80 are NC for ×32
–133
133
425
100
7.5
30
4
TQFP 14 × 20 mm
Copyright © Alliance Semiconductor. All rights reserved.
AS7C3364PFS32A
AS7C3364PFS36A
AS7C3364PFS32A
–100
100
325
10
90
30
5
P. 1 of 11
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
Units
MHz
mA
mA
mA
DQP
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
NC
VDD
ZZ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQP
ns
ns
DDQ
SSQ
SSQ
DDQ
SS
DDQ
SSQ
SSQ
DDQ
b
b
b
b
b
b
b
b
a
a
a
a
a
a
a
a
b
a
/NC
/NC

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as7c3364pfs32a Summary of contents

Page 1

... SSQ 27 54 DDQ / Note: Pins 1,30,51,80 are NC for ×32 AS7C3364PFS32A AS7C3364PFS32A –133 –100 7.5 10 133 100 4 5 425 325 100 Copyright © Alliance Semiconductor. All rights reserved. DDQ DQP / ...

Page 2

... WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High). • Master chip enable CE0 blocks ADSP, but not ADSC. ASAS7C3364PFS32A and ASAS7C3364PFS36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × TQFP package. ...

Page 3

... Symbol Min –0.5 DD DDQ V –0 –0 – – OUT T –65 stg T –65 bias Alliance Semiconductor AS7C3364PFS32A AS7C3364PFS36A 18 DD Max Unit +4 0 0.5 V DDQ 1 +150 C o +135 ...

Page 4

... SSQ V 2.35 DDQ V 0.0 SSQ V 2 –0 2 –0 Alliance Semiconductor AS7C3364PFS32A AS7C3364PFS36A CLK Operation Deselect Deselect Deselect Deselect Deselect Begin read Begin read ...

Page 5

... Min Max Min Max Min Max Min Max Max – GND to V OUT mA 2.65V – 0.7 DDQ = –2 mA 2.35V 1.7 – DDQ Alliance Semiconductor AS7C3364PFS32A AS7C3364PFS36A Symbol Typical Units 46 C/W JA 2.8 C/W JC –150 –133 –100 – 2 – 2 – 2 – 2 – ...

Page 6

... ADSPS t 1.5 – 1.5 – ADSCS t 0.5 – 0.5 – ADVH t 0.5 – 0.5 – ADSPH t 0.5 – 0.5 – ADSCH Falling input Alliance Semiconductor AS7C3364PFS32A AS7C3364PFS36A –133 –100 Notes Min Max Min Max Unit – 133 – 100 MHz 7.5 – 10 – – 12 – ns – 4.0 – 5.0 ns – ...

Page 7

... Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW. BW[a:d] is don’t care. 2/1/01 ® t CYC ADSCH LOAD NEW ADDRESS HZOE t OH ADV INSERTS WAIT STATES Q(A2) Q(A2Ý10) Q(A2Ý01) Q(A2Ý10) Q(A2Ý01) Q(A2Ý11) Alliance Semiconductor AS7C3364PFS32A AS7C3364PFS36A t HZC Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3) Q(A3Ý11) Q(A3Ý01) Q(A3Ý10) t HZC ...

Page 8

... CE1 ADV OE Data In D(A1) Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW. 2/1/01 ® t CYC ADV SUSPENDS BURST D(A2) D(A2Ý01) D(A2Ý01) D(A2Ý10) Alliance Semiconductor AS7C3364PFS32A AS7C3364PFS36A t ADSCS t ADSCH ADSC LOADS NEW ADDRESS ADVS t ADVH D(A2Ý ...

Page 9

... Note: Ý = XOR when MODE = HIGH/No Connect; Ý = ADD when MODE = LOW. 2/1/01 ® t CYC ADVS t ADVH D(A2 HZOE LZC t CD Q(A1) Q(A1) Alliance Semiconductor AS7C3364PFS32A AS7C3364PFS36A LZOE t OE Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11 ...

Page 10

... V = 1.5V L for 3.3V I/ DDQ for 2.5V I/O Figure B: Output load (A) at any given temperature and voltage. LZC Alliance Semiconductor AS7C3364PFS32A AS7C3364PFS36A Thevenin equivalent: +3.3V for 3.3V I/O; +2.5V for 2.5V I/O 317 D OUT 5 pF* 351 GND *including scope and jig capacitance Figure C: Output load( ...

Page 11

... Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. ® –150 MHz –133 MHz AS7C3364PFS32A-133TQC AS7C3364PFS32A-133TQI AS7C3364PFS36A-133TQC AS7C3364PFS36A-133TQI PF S 32/ Alliance Semiconductor AS7C3364PFS32A AS7C3364PFS36A –100 MHz AS7C3364PFS32A-100TQC AS7C3364PFS32A-100TQI AS7C3364PFS36A-100TQC AS7C3364PFS36A-100TQI A –XXX TQ C ...

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