as7c33128pfs32a-166tqi Alliance Memory, Inc, as7c33128pfs32a-166tqi Datasheet - Page 3

• Manufacturer Part Number: as7c33128pfs32a-166tqi
• Description: 3.3v 128k 32/36 Pipeline Burst Synchronous Sram
• Manufacturer: Alliance Memory, Inc

Signal descriptions
Absolute maximum ratings
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
CLK
A0–A16
DQ[a,b,c,d] I/O SYNC
CE0
CE1, CE2
ADSP
ADSC
ADV
GWE
BWE
BW[a,b,c,d] I
OE
LBO
FT
ZZ
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias
Signal
Parameter
2/1/01
I
I
I
I
I
I
I
I
I
I
I
I
I
I/
O
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
default =
HIGH
STATIC
ASYNC
Properties
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock
edges when ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
Advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d]
control write enable.
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:d] are inactive the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This signal is internally pulled High.
Flow-through mode.When low, enables single register flow-through mode. Connect to V
if unused or for pipelined operation.
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Description
Alliance Semiconductor
V
V
V
P
I
T
T
Symbol
OUT
D
stg
bias
DD
IN
IN
, V
DDQ
®
–0.5
–0.5
–0.5
–
–
–65
–65
Min
+4.6
V
V
1.8
50
+150
+135
Max
DD
DDQ
+ 0.5
+ 0.5
7C33128PFS32A
7C33128PFS36A
V
V
V
W
mA
o
o
Unit
C
C
P. 3 of 11
18
DD