am29lv040b Meet Spansion Inc., am29lv040b Datasheet - Page 12

• Manufacturer Part Number: am29lv040b
• Description: 4 Mbit 512 K ? 8-bit
• Manufacturer: Meet Spansion Inc.

L = Logic Low = V
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Sector protection/unprotection method intended only
for programming equipment requires V
pin A9 and OE#. This method is compatible with pro-
grammer routines written for earlier 3.0 volt-only AMD
flash devices. Publication number 22168 contains
further details; contact an AMD representative to
request a copy.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadver tent writes (refer to Table 4 for
command definitions). In addition, the following hard-
ware data protection measures prevent accidental
12
Manufacturer ID: AMD
Device ID: Am29LV040B
Sector Protection Verification
Description
IL
, H = Logic High = V
Table 3. Am29LV040B Autoselect Codes (High Voltage Method)
CE#
IH
L
L
L
, SA = Sector Address, X = Don’t care.
ID
OE#
on address
L
L
L
D A T A
WE#
H
H
H
Am29LV040B
A18
A16
SA
to
X
X
S H E E T
erasure or programming, which might otherwise be
caused by spurious system level signals during V
power-up and power-down transitions, or from system
noise.
Low V
When V
accept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent uninten-
tional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
A15
A10
IL
to
X
X
X
, CE# = V
CC
V
V
V
A9
ID
ID
ID
CC
Write Inhibit
is less than V
A8
A7
IH
to
X
X
X
or WE# = V
IL
LKO
A6
and OE# = V
L
L
L
CC
. The system must provide the
is greater than V
A5
A2
to
X
X
X
LKO
IH
. To initiate a write cycle,
A1
H
21354E4 October 11, 2006
L
L
, the device does not
IH
during power up, the
A0
H
L
L
LKO
(unprotected)
(protected)
.
DQ7
DQ0
01h
4Fh
01h
00h
to
CC
CC
CC