a290011tx-90f AMIC Technology Corporation, a290011tx-90f Datasheet - Page 6

• Manufacturer Part Number: a290011tx-90f
• Description: 128k X 8 Bit Cmos 5.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMIC Technology Corporation

Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
selects the device.
array data to the output pins.
the time during read operation. The internal state machine
is set for reading array data upon device power-up, or after
a hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to
the AC Read Operations table for timing specifications and
to the Read Operations Timings diagram for the timing
waveforms, l
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive
to V
sector, multiple sectors, or the entire device. The Sector
Address Tables indicate the address range that each
sector occupies. A "sector address" consists of the address
inputs required to uniquely select a sector. See the
"Command Definitions" section for details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register
(which is separate from the memory array) on I/O
Standard read cycle timings apply in this mode. Refer to
the
Sequence" sections for more information.
I
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.
(December, 2004, Version 1.3)
CC2
CE
IL
in the Characteristics table represents the active
, and
"Autoselect
7
and
- I/O
OE
OE
CC1
0
. Standard read cycle timings and I
to V
in the DC Characteristics table represents
pins to V
Mode"
IH
OE
. An erase operation can erase one
is the output control and gates
IL
.
and
CE
WE
is the power control and
"Autoselect
should remain at V
WE
Command
and
CC
7
- I/O
IH
read
CE
all
0
.
5
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of the
The device enters the CMOS standby mode when the
& RESET pins (
V
range than V
when
A290011) is held at VCC±0.5V. The device requires the
standard access time (t
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
standby current specification.
Output Disable Mode
When the
disabled. The output pins are placed in the high impedance
state.
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET pin low for at least a period of t
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.
The RESET pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
RESET
OE
CC3
CC
± 0.5V. (Note that this is a more restricted voltage
input.
in the DC Characteristics tables represents the
CE
: Hardware Reset Pin (N/A on A290011)
is held at V
OE
IH
.) The device enters the TTL standby mode
input is at V
CE
A29001/A290011 Series
only on A290011) are both held at
CE
IH
AMIC Technology, Corp.
, while RESET (Not available on
) before it is ready to read data.
IH
, output from the device is
RP
, the device
CE