m52s32321a Elite Semiconductor Memory Technology Inc., m52s32321a Datasheet - Page 7

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m52s32321a

Manufacturer Part Number
m52s32321a
Description
512k X 32bit X 2banks Synchronous Dram
Manufacturer
Elite Semiconductor Memory Technology Inc.
Datasheet
ESMT
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Note :
Elite Semiconductor Memory Technology Inc.
Function
Address
A8
A9
0
0
1
1
0
1
Write Burst Length
A7
1. RFU(Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256 bit) is available only at sequential mode of burst type.
0
1
0
1
Test Mode
Mode Register Set
Single Bit
BA
Length
0
Burst
Reserved
Reserved
Reserved
Type
A10/AP
RFU
A6
0
0
0
0
1
1
1
1
A5
CAS Latency
0
0
1
1
0
0
1
1
W.B.L
A9
A4
0
1
0
1
0
1
0
1
A8
Reserved
Reserved
Reserved
Reserved
Reserved
Latency
TM
1
2
3
A7
A3
A6
0
1
Burst Type
CAS Latency
Sequential
Interleave
A5
Type
A4
Full Page Length : 256
A2
0
0
0
0
1
1
1
1
Revision : 1.5
BT
Publication Date : Jan. 2009
A3
M52S32321A
A1
0
0
1
1
0
0
1
1
A2
Burst Length
Burst Length
A0
0
1
0
1
0
1
0
1
A1
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
BT = 0
A0
1
2
4
8
7/29
BT = 1
1
2
4
8

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