gal22v10d-10lr-883 Lattice Semiconductor Corp., gal22v10d-10lr-883 Datasheet - Page 6

• Manufacturer Part Number: gal22v10d-10lr-883
• Description: High Performance E2 Cmos Pld Generic Array Logic? Gal Data Sheets
• Manufacturer: Lattice Semiconductor Corp.

3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
fmax Descriptions
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
Test Condition
A
B
C
Active High
Active Low
Active High
Active Low
f
max with External Feedback 1/(
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
LOGIC
ARRAY
LOGIC
ARRAY
t
su +
f
t
max with No Feedback
su
t
h
390
390
390
R
1
REGISTER
REGISTER
CLK
CLK
750
750
750
750
750
R
3ns 10% – 90%
2
t
GND to 3.0V
t
See Figure
co
su+
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
6
Specifications GAL22V10/883
FROM OUTPUT (O/Q)
UNDER TEST
*C
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
L
f
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
max with Internal Feedback 1/(
LOGIC
ARRAY
R
2
t
cf
t
+5V
pd
REGISTER
CLK
R
1
t
su+
C *
L
t
TEST POINT
cf)