isplsi2064a-80ljn84i Lattice Semiconductor Corp., isplsi2064a-80ljn84i Datasheet - Page 7

• Manufacturer Part Number: isplsi2064a-80ljn84i
• Description: In-system Programmable High Density Pld
• Manufacturer: Lattice Semiconductor Corp.

Note: Calculations are based upon timing specifications for the ispLSI 2064/A-125L.
ispLSI 2064/A Timing Model
GOE 0,1
Derivations of
Ded. In
Y0,1,2
I/O Pin
Reset
(Input)
t
t
t
su
h
co
3.5 ns
2.6 ns
9.4 ns
I/O Delay
#21
#20
=
=
=
=
=
=
=
=
=
=
=
=
t
I/O Cell
su,
Logic + Reg su - Clock (min)
(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.2 + 1.3 + 6.0) + (0.8) - (0.2 + 1.3 + 3.3)
Clock (max) + Reg h - Logic
(
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.2 + 1.3 + 5.6) + (3.0) - (0.2 + 1.3 + 6.0)
Clock (max) + Reg co + Output
(
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.2 + 1.3 + 5.6) + (0.2) + (0.8 + 1.2)
t
t
t
io +
io +
io +
t
h and
t
t
t
grp +
grp +
grp +
t
t
t
co from the Product Term Clock
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
Reg 4 PT Bypass
io +
t
XOR Delays
#33, 34,
Control
PTs
#25, 26, 27
Feedback
orp +
t
20 PT
35
grp +
t
#24
grp +
Comb 4 PT Bypass #23
7
t
OE
RE
CK
ob)
t
Specifications ispLSI 2064/A
ptck(min))
Table 2- 0042A-2064
t
20ptxor)
GLB
1
GLB Reg Bypass
D
RST
GLB Reg
Delay
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#37
#36
#40, 41
0491/2064
#38,
39
I/O Cell
(Output)
I/O Pin