ht827a0 Holtek Semiconductor Inc., ht827a0 Datasheet - Page 12

• Manufacturer Part Number: ht827a0
• Description: 8-bit Microcontroller With Voice Rom
• Manufacturer: Holtek Semiconductor Inc.

Status register - STATUS
This 8-bit register (0AH) consists of a zero flag
(Z), carry flag (C), auxiliary carry flag (AC),
overflow flag (OV), power down flag (PD) and
watchdog time-out flag (TO). It also records the
status information and controls the operation
sequence.
Except the TO and PD flags, bits in the status
register can be altered by instructions similar to
other registers. Any data written into the status
register will not change the TO or PD flag. Opera-
tions related to the status register may yield dif-
ferent results from those intended. The TO and
PD flags can be altered only by a watchdog timer
overflow, chip power-up, clearing the watchdog
time or executing the ²HALT² instruction.
The Z, OV, AC and C flags generally reflect the
statuses of the latest operations.
The status register will not be pushed onto the
stack automatically on entering the interrupt
sequence or executing the subroutine call. If the
status contents are important and the subrou-
tine may corrupt the status register, the pro-
grammer must take precautions and save it
properly.
Labels
AC
OV
PD
TO
¾
¾
C
Z
Bits
0
1
2
3
4
5
6
7
C is set if an operation results in a carry during an addition operation or if a bor-
row does not take place during a subtraction operation; otherwise C is cleared. It
is also affected by a rotate through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or if
no borrow from the high nibble into the low nibble in subtraction takes place;
otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV is set if an operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa, otherwise OV is cleared.
PD is cleared by a system power-up or executing the ²CLR WDT² instruction.
PD is set by executing the ²HALT² instruction.
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² in-
structions. TO is set by a WDT time-out.
Undefined, read as ²0²
Undefined, read as ²0²
STATUS register
12
Interrupt
The HT827A0 provides an external interrupt in
addition to two internal timer/event counter in-
terrupts. The interrupt control register (INTC;
0BH) includes interrupt control bits to set the
enable/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all
the other interrupts will be blocked (by clear-
ing the EMI bit). This scheme may prevent any
further interrupt nesting. Other interrupt re-
quests may happen during this interval but
only the interrupt request flag is recorded. If
an interrupt needs servicing within the ser-
vice routine, the programmer may set the EMI
bit and the corresponding bit of INTC, allow-
ing interrupt nesting. If the stack is full, the
interrupt request will not be acknowledged till
the SP is decremented, whether or not the re-
lated interrupt is enabled. If immediate ser-
vice is desired, the stack has to be prevented
from becoming full.
All these interrupts have a wakeup capability.
As an interrupt is serviced, a control transfer
occurs by pushing the program counter onto the
Function
March 15, 2000
HT827A0