ht82j97e Holtek Semiconductor Inc., ht82j97e Datasheet - Page 11

• Manufacturer Part Number: ht82j97e
• Description: Ht82j97e/ht82j97a -- Usb Joystick Encoder 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

sume execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt re-
sponse takes place. If an interrupt request flag is set to
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are four ways in which a reset can occur:
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that resets only the program counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the initial condition when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
tem resets (power-up, WDT time-out or RES reset) or
the system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
Rev. 1.50
1 before entering the HALT mode, the wake-up func-
chip resets .
TO PDF
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
USB reset
0
u
0
1
1
0
u
1
u
1
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
RESET Conditions
SYS
(system clock
11
The functional unit chip reset status are shown below.
Program Counter
Interrupt
Prescaler
WDT
Timer/event Counter Off
Input/output Ports
Stack Pointer
Reset Configuration
Reset Timing Chart
Reset Circuit
HT82J97E/HT82J97A
000H
Disable
Clear
Clear. After master reset,
WDT begins counting
Input mode
Points to the top of the stack
October 19, 2005