ht82v842 Holtek Semiconductor Inc., ht82v842 Datasheet
ht82v842
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ht82v842 Summary of contents
Page 1
... Black level neutralizer, target setting: 16~127LSB · Built-in serial interface General Description The HT82V842 is a CMOS single-chip signal process- ing device for CCD area sensors. It consists of a clamp circuit, Correlated Double Sampler (CDS), Programma- ble Gain Amplifier (PGA), reference voltage generator, Block Diagram Rev ...
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... Power down control (Active low) 35 RESET I Reset signal (Active low) 36 OUTCK I Clock source for ADC output 37~41, 44~48 DO0~DO9 O Digital output from ADC Rev. 1. Description via 0.1mF SS via 0.1mF SS via 0.1mF SS via 0.1mF~1mF (by applications HT82V842 July 15, 2004 ...
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... Relative gain 3V 0 0.047 ¾ ¾ 3V ¾ ¾ 3V ¾ ±0 =20MHz S ¾ ¾ 3V ¾ ¾ 3V ¾ 3V 1.25 1.4 ¾ 3V 1.55 1.65 ¾ 3V 1.05 1.15 3 HT82V842 Ta=25°C Max. Unit ¾ ¾ 0. ¾ mA 200 ¾ ¾ ¾ ¾ ¾ V P-P ¾ V P-P 1.9 V ¾ ...
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... Active ® High-Z ¾ ¾ 3.0V High-Z® Active ¾ ¾ 3.0V 4 HT82V842 Typ. Max. Unit ¾ 127 LSB ¾ 127 LSB ¾ 1 LSB V =0V, Ta=25°C SS Typ. Max. Unit ¾ 20 MHz ¾ ¾ ns ¾ ¾ ...
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... The DC clamping (CCDCLP) is allowed while the OBP pin is low. The black level cancellation is available at ²ADIN signal to PGA² mode. The black level cancella- tion is available at the ADCLP period in this mode. The clamping function and black level canceling function are done simultaneously. 5 HT82V842 July 15, 2004 ...
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... Black Level Calibration Timing High-speed Black Level Cancellation The HT82V842 has a high speed black level cancella- tion function, which by means of a register setting en- hances the settling speed within a fixed period from access to the serial interface. It increases the gain of the setting DAC within a fixed period and in turn increases the charge/discharge current to the OBCAP capacitor ...
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... Each bit is fetched at the rising edge of the CS input. Keep CS to high when not access HT82V842 prohibited to write to a non-defined ad- dress. When a data length is below 16 bits, the data is not executed. ...
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... ADC code at black level (1 LSB step) Register Map Ö Ö ------ Ö Ö Ö ------ ------ ------ Ö ------------------------------------------------------------------------ 8 HT82V842 Ö Ö Ö ------ --------------------------- July 15, 2004 ...
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... Both of S/H and enable inversion 0 0 Monitor off 0 1 CDS signal to monitor 1 0 PGA output monitor 1 1 Output REFIN and CCDIN 0 CDS gain=odB 1 CDS gain=6.02dB 0 CDS gain=12.04dB 1 CDS gain=-1.94dB 0 Boost control on 1 Always high gain 9 HT82V842 July 15, 2004 ...
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... HT82V842 PGA Gain (dB) 0 0.046 0.093 0.142 0.187 ¯ 2.915 2.962 3.011 3.056 ¯ 5.972 6.021 6.058 ¯ 9.031 ¯ 11.994 12.041 12.087 ¯ 15.05 ¯ ...
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... HT82V842 HEX Forbidden 1 ¯ ¯ 20 ¯ 40 ¯ July 15, 2004 ...
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... ADCK inversion: At Mode 1 register D6=1; 6.0 clk delay In ADIN input mode, the above mentioned register setting is available. At ADIN (PGA) input Mode 1 register D5=0 and D4=1, digital data output is delayed by 2 clks. ADCK Clock Waveform Rev. 1.00 ADC Direct Input Chart OUTCK Timing Chart 12 HT82V842 July 15, 2004 ...
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... Test Conditions Min. Typ. VDD Conditions ¾ ¾ 3.0V ¾ 3.0V 40 ¾ 3.0V 40 ¾ 3.0V 20 ¾ 3.0V 20 ¾ 3.0V 30%®70% ¾ 3.0V 70%®30% ¾ ¾ 3.0V Serial I/F Timing Chart 13 HT82V842 V =0V, Ta=25°C) SS Max. Unit ¾ 10 MHz ¾ ¾ ns ¾ ¾ ns ¾ ¾ ns ¾ ¾ ns ¾ ¾ ¾ 16 ...
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... Pixel Data Readout Sequence (2): End of Conversion Clock Timing Variations by Register Setting Clock timing variations when it is inverted by register settings. · No inversion Mode 1 register D6=0, Mode 2 register D2=0; Default Pulse Control (Default: No Inversion) Rev. 1.00 HT82V842 14 July 15, 2004 ...
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... Mode 1 register D6=1, Mode 2 register D2=0 Pulse Control (ADCK Inversion) · SHR & SHD inversion Mode 1 register D6=0, Mode 2 register D2=1 Pulse Control (SHR & SHD Inversion) · ADCK, SHR & SHD inversion Mode 1 register D6=1, Mode 2 register D2=1 Pulse Control (ADCK, SHR & SHD Inversion) Rev. 1.00 HT82V842 15 July 15, 2004 ...
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... Pin 18 can also connect to ground with a 4.7kW resistor. Note: ²**² The capacitor connects to OBCAP pin maybe need adjust by user¢s applications from 0.1mF~1mF typically. Rev. 1.00 HT82V842 July 15, 2004 ...
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... Package Information 48-pin LQFP (7´7) Outline Dimensions Symbol Min. A 8.90 B 6.90 C 8.90 D 6.90 ¾ E ¾ 1.35 ¾ H ¾ 0.45 K 0.10 a 0° Rev. 1.00 HT82V842 a Dimensions in mm Nom. Max. ¾ 9.10 ¾ 7.10 ¾ 9.10 ¾ 7.10 ¾ 0.50 ¾ 0.20 ¾ 1.45 ¾ 1.60 ¾ 0.10 ¾ 0.75 ¾ 0.20 ¾ 7° 17 July 15, 2004 ...
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... Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT82V842 18 July 15, 2004 ...