sip42104 Vishay, sip42104 Datasheet - Page 5

• Manufacturer Part Number: sip42104
• Description: Sip42104 - H-bridge Driver And Pulse Width Controller For Digital Camera Micro Modules
• Manufacturer: Vishay

TIMING DIAGRAM
DETAILED OPERATIONAL DESCRIPTION
SiP42104 is an easy to use integrated H-bridge driver and
programmable output pulse width controller IC intended for
digital camera micro module focus mode applications. The
IC is designed to drive a solenoid of several hundred
micro-Henrys and operates over the supply range of 2.3 to
4.2 V. Both H-bridge output can source and sink up to
250
shoot-through via M1 to M2 or M3 to M4 in the H-bridge and
is guaranteed by design.
In the absence of any edge transitions at the input pin, the IC
is in the power-down mode with the H-bridge outputs at high
impedance drawing only sub micro-amp of leakage current
from the supply.
The input pin is CMOS logic level and has typical 1.75 µA
pull-down current, the input pin is buffered by a Schmitt
trigger with the threshold level of 1.1 V and typical hysteresis
of 280 mV. A logic transition closes SW2 and initiates the
H-Bridge output turn-on for duration set by the external RC
time constant. The logic level transition is latched in the
device and this logic level transition determines which of the
H-Bridge output MOSFETs turns on. If the logic transition is
rising from ground to V
present for at least 2 µs, then M1 and M4 will turn on, M2 and
M3 will turn off. This means that OUT1 will go high and OUT2
will go low. Conversely, a falling logic transition is from V
to ground, with the low level being present for 2 µs, will turn
on M2 and M3, M1 and M4 will turn off. Once the input
transition is latched, SiP42104 will ignore any input spurious
transition until the RC pin time out is completed. An internal
deglitch filter following the input buffer prevents SiP42104
from being accidentally triggered by the input pulse less than
300 ns duration.
Document Number: 74633
S-80224-Rev. C, 04-Feb-08
mA.
The
break-before-make
DD
, with the high condition being
Input Control Logic
Input Control Logic
Output Current
V
OUT1
delays
T
RC
T
EDGE
= 1.3 x RC
< 100 ns
prevents
DD
Figure 4.
T > 2 µs
S S
A positive edge transition on the input pin also initiates
SiP42104 to charge the RC pin to V
pre-charge period lasts for approximately 30 µs. When the
pre-charge period is completed, SW1 will turn off and the
external capacitor begins to discharge via the external
resistor. The timer and pulse width controller sense the
voltage on RC pin. When the voltage on the RC pin falls to
V1 (0.27 x V
terminate the timeout and turn off the relevant H-bridge
outputs. This yields and output pulse width given by:
SiP42104 H-bridge output typically drives an inductive load.
When output are turned off after the RC timeout, the current
will still be flowing in the inductive load. To prevent the load
current from forward biasing the body diodes of the output
MOSFETs, both H-bridge low-side MOSFETs M2 and M4
will turn on briefly to allow the inductive load current to
discharge to zero. When the voltage on the RC pin has fallen
to V2 (0.23 x V
Where R1 is the built-in resistor of 1.1 kΩ.
Following this discharge time period, SW2 and all H-bridge
output MOSFETs are turned off. SiP42104 powers down to
its low quiescent current state. SiP42104 will remain in this
state until the next input transition logic applied to the input
pin to wake up.
T
EDGE
V
OUT2
DD
DD
< 100 ns
T
DISCHARGE
). The timer and pulse width controller
). This yields a discharge time:
T
RC
T
OUTPUT
= 1.3 x RC
= 0.13 x C x R1
= 1.3 x RC
Vishay Siliconix
DD
SiP42104
via SW1. This
www.vishay.com
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