adum1250 Analog Devices, Inc., adum1250 Datasheet - Page 10

• Manufacturer Part Number: adum1250
• Description: Hot Swappable Dual I2c Isolators
• Manufacturer: Analog Devices, Inc.

ADuM1250/ADuM1251
APPLICATION NOTES
FUNCTIONAL DESCRIPTION
The ADuM1250/ADuM1251 interfaces on each side to a
bidirectional I
two unidirectional channels communicating in opposing
directions via a dedicated iCoupler isolation channel for each.
One channel (the bottom channel of each channel pair shown
in Figure 6) senses the voltage state of the Side 1 I
transmits its state to its respective Side 2 I
Both the Side 1 and the Side 2 I
to an I
on either causes the opposite pin to be pulled low enough to
comply with the logic low threshold requirements of other I
devices on the bus. Avoidance of I
by an input low threshold at SDA
least 50 mV less than the output low signal at the same pin. This
prevents an output logic low at Side 1 being transmitted back to
Side 2 and pulling down the I
Since the Side 2 logic levels/thresholds are standard I
multiple ADuM1250/ADuM1251 devices connected to a bus by
their Side 2 pins can communicate with each other and with
other devices having I
However, since the Side 1 pin has a modified output level/input
threshold, this side of the ADuM1250/ADuM1251 can only
communicate with devices conforming to the I
other words, Side 2 of the ADuM1250/ADuM1251 is I
compliant while Side 1 is only I
The output logic low levels are independent of the V
V
independent of V
Side 2 is designed to be at 0.3 V
requirements. The Side 1 and Side 2 pins have open-collector
outputs whose high levels are set via pull-up resistors to their
respective supply voltages.
GND
1
SDA
SCL
V
Here a distinction is made between I
compatibility refers to situations in which a component's logic levels do not
necessarily meet the requirements of the I
component to communication with an I
refers to situations in which a component's logic levels meet the
requirements of the I
DD1
DD2
1
1
1
voltages. The input logic low threshold at Side 1 is also
1
2
3
4
2
C bus operating in the 3.0 V to 5.5 V range. A logic low
2
DECODE
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C signal. Internally, the I
Figure 6. ADuM1250 Block Diagram
DD1
2
C specification.
. However, the input logic low threshold at
2
C compatibility
2
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C bus.
2
2
2
DD2
C compatibility and I
C-compatible.
C pins are designed to interface
1
2
2
, consistent with I
or SCL
C-compliant device. I
C bus contention is ensured
2
C specification but still allow the
1
.
2
C interface is split into
2
1
C pin.
guaranteed to be at
8
7
6
5
2
V
SDA
SCL
GND
C standard. In
DD2
2
C compliance. I
2
C pin and
2
2
2
2
2
DD1
C compliance
2
C
C values,
2
C-
R2
C
and
L
2
R2
Rev. 0 | Page 10 of 12
C
C
L
2
C
STARTUP
Both the V
feature to prevent the signal channels from operating unless
certain criteria are met. This avoids the possibility of input logic
low signals from pulling down the I
power-up/power-down.
The two criteria that must be met in order for the signal
channels to be enabled are as follows:
x
x
Until both of these criteria are met for both supplies, the
ADuM1250/ADuM1251 outputs are pulled high, ensuring a
startup that avoids any disturbances on the bus. Figure 7 and
Figure 8 illustrate the supply conditions for fast and slow input
supply slew rates.
OPERATING SUPPLY, 3.0V
MIN. VALID SUPPLY, 2.5V
Both supplies must be at least 2.5 V.
At least 40 μs must elapse after both supplies exceeded the
internal startup threshold of 2.0 V.
MINIMUM VALID SUPPLY, 2.5V
MIN. RECOMMENDED
MINIMUM RECOMMENDED
OPERATING SUPPLY, 3.0V
Figure 7. Start-Up Condition, Supply Slew Rate >12.5 V/ms
Figure 8. Start-Up Condition, Supply Slew Rate <12.5 V/ms
INTERNAL STARTUP
THRESHOLD, 2.0V
DD1
INTERNAL STARTUP
THRESHOLD, 2.0V
and V
DD2
supplies have an under voltage lockout
2
C bus inadvertently during
40µs
SUPPLY VALID
40µs
SUPPLY VALID