that5171 THAT Corporation, that5171 Datasheet - Page 12

• Manufacturer Part Number: that5171
• Description: High-performance Digital Preamplifier Controller Ic
• Manufacturer: THAT Corporation

Document 600133 Rev 02
CROSSING mode depends on the application. Imme-
diate mode has the advantage of providing immediate
gain updates with deterministic latency and the abil-
ity to synchronize updates between the mic preamp
and subsequent signal processing (e.g. digital inter-
polation of finer steps in gain), whereas ZERO-
CROSSING mode has the advantage of minimizing
glitches and zipper noise.
Serial Peripheral Interface (SPI) Port
SPI Signals
microcontroller host is the Master). The SPI signals
are listed in Table 3. Figure 7 and Table 4 show the
SPI timing parameters.
commands (Figure 8). In a write operation, data is
clocked into the DIN pin, MSB first, on the rising
edge of SCLK.
the DIN pin, MSB first, on the rising edge of SCLK,
and an 8-bit data word is clocked out of the DOUT
pin, MSB first, on the falling edge of SCLK.
SPI Command Format
four bitfields, shown in Table 5.
address, A[2:0], specifies which chip on the SPI bus
is being targeted. The R/W bit specifies whether this
command is a read (0) or write (1) operation. The
3-bit register address, R[2:0], specifies which register
within the 5171 will be read or written. The data
field, D[7:0], carries data for the command.
SPI Registers
within the 5171. The registers and their addresses
are listed in Table 6.
SCLK
CS
DIN
DOUT
The choice between IMMEDIATE vs ZERO-
The 5171 is a Slave device on the SPI bus (the
The SPI protocol consists of 16-bit read and write
In a read operation, address bits are clocked into
SPI read and write commands are comprised of
SPI Read and Write commands access registers
B) Gain is updated on the next zero-crossing or
when the voltage on the TRC pin charges to
0.7*V
The recommended time constant for R
~22mS (e.g. C
DD
t4
-- whichever event occurs first.
t5
t6
Figure 7. SPI Timing.
t2
T
t1
= 1nF and R
t3
Tel: [phone]; Fax: [phone]; Web: www.thatcorp.com
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
t7
Copyright © 2009, THAT Corporation; All rights reserved.
t8
T
t9
= 22MΩ ).
The 3-bit device
t10
t11
T
C
T
Page 12 of 20
is
Param.
CS
SCLK
DIN
DOUT
CS
SCLK
DIN
DOUT
Table 5. SPI command format. (See Figure 8 for timing of
Register Address: R[2:0]
t10
t11
Figure 8. SPI command word formats (read and write).
t1
t2
t3
t4
t5
t6
t7
t8
t9
R[2:0]
D[7:0]
A[2:0]
Field
R/W
HiZ
SCLK cycle time
SCLK low time
SCLK high time
CS setup to SCK rising
DIN setup time
DIN hold time
SCLK rising to DOUT out of tristate
SCLK falling to DOUT valid
SCLK falling to CS inactive
CS inactive to DOUT tristate
CS inactive to SCLK rising
HiZ
100 ~ 111
(See Table 5 for definitions of bitfields.)
Table 4. SPI timing parameters (ns).
A2
A2
000
001
010
011
A1
A1
the bits within these fields.)
A0
A0
Device address
During reset the GPIO[2:0] pins are read
as inputs to establish the device address.
Read/write control
R/W = 0 for read
R/W = 1 for write
Register Address
Specifies which register within the 5171
will be read or written by the command.
Data
For R/W=1 this is the data to be written
For R/W=0 the data is ignored
Table 6. SPI Registers.
Command Word - Write
Command Word - Read
Description
R2
R2
R1
R1
Digital Preamplifier Controller IC
R0
R0
THAT5171 High-Performance
0
0
CHIP ID
GAIN
GPO
CONTROL/STATUS
Reserved
D7
D7
X
Function
D6 D5 D4 D3 D2 D1 D0
D6 D5 D4 D3 D2 D1 D0
X
X
X
Function
X
X X
Min
100
100
40
40
50
15
15
50
5
5
-
X
Max
10
15
20
-
-
-
-
-
-
-
-