a3p250l Actel Corporation, a3p250l Datasheet - Page 103
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a3p250l
Manufacturer Part Number
a3p250l
Description
Proasic3l Low-power Flash Fpgas With Flash*freeze Technology
Manufacturer
Actel Corporation
Datasheet
1.A3P250L.pdf
(188 pages)
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Figure 2-38 • Timing Model and Waveforms
Table 2-144 • Register Delays
CLK
Data
EN
Out
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
PRE
CLR
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
For specific junction temperature and voltage supply levels, refer to
values.
Timing Characteristics
Commercial-Case Conditions: T
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
50%
50%
t
SUE
t
HE
50%
t
CLKQ
50%
t
SUD
0
t
HD
t
50%
PRE2Q
50%
J
50%
t
= 70°C, Worst-Case V
WPRE
Description
A dv a n c e v 0. 4
50%
50%
50%
t
t
RECPRE
WCLR
50%
t
50%
50%
CLR2Q
CC
50%
= 1.14 V
t
RECCLR
ProASIC3L DC and Switching Characteristics
Table 2-6 on page 2-7
50%
t
CKMPWH
t
50%
REMPRE
0.73
0.57
0.00
0.61
0.00
0.53
0.53
0.00
0.30
0.00
0.30
0.30
0.30
0.56
0.56
t
–1
50%
CKMPWL
0.86
0.67
0.00
0.71
0.00
0.63
0.63
0.00
0.35
0.00
0.35
0.34
0.34
0.64
0.64
Std.
for derating
50%
50%
t
REMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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