lfe2-12e-5qn208 Lattice Semiconductor Corp., lfe2-12e-5qn208 Datasheet - Page 331
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lfe2-12e-5qn208
Manufacturer Part Number
lfe2-12e-5qn208
Description
Latticeecp2/m Family Data Sheet
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.LFE2-12E-5QN208.pdf
(386 pages)
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LFE2M100E/SE Logic Signal Connections: 900 fpBGA (Cont.)
Lattice Semiconductor
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
*** These sysCONFIG pins are dedicated I/O pins for configuration. The outpus are actively driven during normal device operation.
****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
Ball Number
U22
N13
N18
V13
V18
J21
W9
K9
R9
J9
Ball/Pad Function
VCCPLL
VCCPLL
VCCPLL
VCCPLL
NC
NC
NC
NC
NC
NC
LFE2M100E/SE
Bank
4-230
-
-
-
-
-
-
-
-
-
-
LatticeECP2/M Family Data Sheet
Dual Function
Pinout Information
Differential
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