a2f500m3b-1csh484 Actel Corporation, a2f500m3b-1csh484 Datasheet - Page 104
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a2f500m3b-1csh484
Manufacturer Part Number
a2f500m3b-1csh484
Description
Actel
Manufacturer
Actel Corporation
Datasheet
1.A2F500M3B-1CSH484.pdf
(170 pages)
- Current page: 104 of 170
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Table 2-98 • I
Figure 2-48 • I2C Timing Parameter Definition
SDA
SCL
Parameter
t
t
Notes:
1. These maximum values are provided for information only. Minimum output buffer resistance values depend on
2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer
3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I
SU;STO
FILT
VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output
buffer
http://www.actel.com/download/ibis/default.aspx.
resistances,
http://www.actel.com/download/ibis/default.aspx.
Microcontroller Subsystem User’s
t
SU;STA
Commercial Case Conditions: T
resistances,
STOP setup time
Maximum spike width filtered
2
C Characteristics
S
use
t
HD;STA
Definition
t
the
LOW
use
T
RISE
3
corresponding
the
t
Guide.
HIGH
corresponding
t
HD;DAT
T
FALL
J
= 85ºC, V
IBIS
t
SU;DAT
IBIS
DD
models
Condition
= 1.425 V, –1 Speed Grade (continued)
models
–
–
located
2
located
C) Peripherals section in the
on
on
the
the
Value
50
1
Actel
Actel
t
SU;STO
P
website
website
SmartFusion
pclk cycles
Unit
ns
at
at
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