en5322 Enpirion, en5322 Datasheet - Page 12

• Manufacturer Part Number: en5322
• Description: 2 A Voltage Mode Synchronous Buck Pwm Dc-dc Converter With Integrated Inductor
• Manufacturer: Enpirion

March 2008
If the external voltage divider option is chosen,
use 340 kΩ, 1% or better for the upper resistor
Ra
kΩ is given as:
Where V
also be a 1% or better resistor.
Input and Output Capacitor Selection
Low ESR MLC capacitors with X5R or X7R or
equivalent dielectric should be used for input
and output capacitors. Y5V or equivalent
dielectrics lose too much capacitance with
frequency,
Therefore, they are not suitable for switch-
mode DC-DC converter filtering, and must be
avoided.
A 10 µF, 10 V, 0805 MLC capacitor is needed
on PVIN for all applications. A 1 µF, 10 V, 0402
MLC capacitor on AVIN is needed for high
frequency bypass to ensure clean chip supply
for optimal performance.
A 47 µF, 6.3 V, 1206 MLC capacitor is
recommended
applications. The output ripple can be reduced
by approximately 50% by using 2 x 22 µF,
6.3V, 0805 MLC capacitors rather than 1 x 47
µF.
Table 2. Recommended input and output capacitors
C
POK Pull Up Resistor Selection
POK can be pulled up through a resistor to any
voltage source as high as V
way is to connect POK to the power input of
the converter through a resistor. A 100 kΩ pull
up resistor is typically recommended for most
©Enpirion 2008 all rights reserved, E&OE
Rb
C
OUT
IN
.
=
Then the value of the bottom resistor Rb in
V
Description
OUT
47µF, 6.3V,
10µF, 10V,
X5R, 10%,
X5R, 20%,
204
OUT
0805
1206
−
0
6 .
is the output voltage. Rb should
DC
k
Ω
on
Taiyo Yuden
Murata
Panasonic
Taiyo Yuden
Murata
Kemet
bias,
Mfg.
the
and
output
ECJ-2FB1A106K
C1206C476M9PACTU
LMK212BJ106KG
GRM21BR71A106KE51L
JMK316BJ476ML
GRM31CR60J476ME19L
IN.
The simplest
temperature.
P/N
for
most
12
applications for minimal current drain from the
voltage source and good noise immunity. POK
can sink up to 5mA.
Layout Considerations
Proper layout and placement of external
components is critical to optimal functioning of
the converter and for minimizing radiated and
conducted noise.
Follow
demonstrated on the EN5322 customer eval
boards:
1. Input and output capacitors should be
2. A row of vias connecting these capacitors’
3. Avoid adding a test pin or test pad for
4. There should be as many vias as possible
5. Keep the input and output current loops
6. Connect the VSENSE trace to the last
placed on the same side of the PCB as
the EN5322 and immediately adjacent to
their respective pins on the package. To
minimize parasitic inductances, the traces
for making these connections should be
as short and wide as possible.
ground pads to the PCB GND plane
should be placed along the edge of the
capacitor ground copper closest to the
positive
should start as close to the device as
possible and continue underneath the
capacitors.
NC(SW) pins on the PCB. Doing so can
compromise the GND plane and result in
degradation of the performance.
connecting the thermal pad under the
device to the PCB GND plane for best
thermal performance. Ideally, the vias
should have a drill diameter of 0.33 mm
(10 mils) with at least 1 oz copper plating
in the barrel.
separate from each other as much as
possible. Keep sensitive signals on the
PCB away from the power supply circuit.
local output capacitor. Make sure the
trace inductance between the output
capacitors and the sensing point is
minimized. The VSENSE trace should
also be kept away from noisy signals that
can contaminate it.
these
capacitor
layout
pads.
www.enpirion.com
guidelines
These
EN5322QI
vias
as