en5311qi-e Enpirion, en5311qi-e Datasheet - Page 12

• Manufacturer Part Number: en5311qi-e
• Description: 1a Synchronous Buck Regulator With Integrated Inductor
• Manufacturer: Enpirion

the thermal pad, to the PCB ground on layer 2 (1
figure shows the layout with the components populated. Note the placement of the vias per
recommendation 3.
Figure 8. Example layout showing PCB top layer, as well as demonstrating use of vias from input, output filter
capacitor local grounds, and thermal pad, to PCB system ground.
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Enpirion has developed a break-through in package technology that utilizes the lead frame as part of
the electrical circuit. The lead frame offers many advantages in thermal performance, in reduced
electrical lead resistance, and in overall foot print. However, it does require some special
considerations.
As part of the package assembly process, lead frame construction requires that for mechanical
support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal
passives are attached. This results in several small pads being exposed on the bottom of the
package.
Only the large thermal pad and the perimeter pin pads are to be mechanically or electrically
connected to the PC board. The PCB top layer under the EN5311QI should be clear of any metal
except for the large thermal pad. The “grayed-out” area in Figure 9 represents the area that should
be clear of any metal (traces, vias, or planes), on the top layer of the PCB.
NOTE: Clearance between the various exposed metal pads, the thermal ground pad, and the
perimeter pins, meets or exceeds JEDEC requirements for lead frame package construction (JEDEC
MO-220, Issue J, Date May 2005). The separation between the large thermal pad and the nearest
adjacent metal pad or pin is a minimum of 0.20mm, including tolerances. This is shown in Figure 10.
©Enpirion 2009 all rights reserved, E&OE
03799
Thermal Vias to Ground Plane
Thermal Vias to Ground Plane
Vias to Ground Plane
Vias to Ground Plane
11/24/2009
st
12
layer below PCB surface). The right side of the
C
C
IN
IN
C
C
OUT
OUT
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Package
Package
Outline
Outline
EN5311QI
Rev:B