74AHC86PW,118 NXP Semiconductors, 74AHC86PW,118 Datasheet

IC QUAD 2IN EXCL OR GATE 14TSSOP

74AHC86PW,118

Manufacturer Part Number
74AHC86PW,118
Description
IC QUAD 2IN EXCL OR GATE 14TSSOP
Manufacturer
NXP Semiconductors
Series
74AHCr
Datasheet

Specifications of 74AHC86PW,118

Number Of Circuits
4
Package / Case
14-TSSOP
Logic Type
XOR (Exclusive OR)
Number Of Inputs
2
Current - Output High, Low
8mA, 8mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Product
OR
Logic Family
AHC
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Propagation Delay Time
3.4 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4542-2
74AHC86PW-T
74AHC86PW-T
935263564118
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74AHC86D
74AHCT86D
74AHC86PW
74AHCT86PW
74AHC86BQ
74AHCT86BQ
Ordering information
Package
Temperature range
40 C to +125 C
40 C to +125 C
40 C to +125 C
The 74AHC86; 74AHCT86 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74AHC86; 74AHCT86 provides a 2-input exclusive-OR function.
74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
Rev. 02 — 15 November 2007
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accepts voltages higher than V
For 74AHC86 only: operates with CMOS input levels
For 74AHCT86 only: operates with TTL input levels
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Name
SO14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5
CC
3
0.85 mm
Product data sheet
Version
SOT108-1
SOT402-1
SOT762-1

Related parts for 74AHC86PW,118

74AHC86PW,118 Summary of contents

Page 1

Quad 2-input EXCLUSIVE-OR gate Rev. 02 — 15 November 2007 1. General description The 74AHC86; 74AHCT86 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard ...

Page 2

... NXP Semiconductors 4. Functional diagram Fig 1. Logic symbol A B Fig 2. Logic diagram (one gate) 74AHC_AHCT86_2 Product data sheet 74AHC86; 74AHCT86 mna787 Y mna788 Fig 3. IEC logic symbol Rev. 02 — 15 November 2007 Quad 2-input EXCLUSIVE-OR gate mna786 © NXP B.V. 2007. All rights reserved. ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74AHC86 2A 4 74AHCT86 GND 7 Fig 4. Pin configuration SO14, TSSOP14 5.2 Pin description Table 2. Pin description Symbol Pin Description data input 10, 13 data input data outputs GND 7 ground ( supply voltage CC 6. Functional description [1] Table 3. Function table ...

Page 4

... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I I input clamping current IK I output clamping current OK I output current O I supply current ...

Page 5

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions For type 74AHC86 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 4.0 mA 8.0 mA LOW-level output voltage 4.0 mA 8.0 mA input leakage GND ...

Page 6

... NXP Semiconductors Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current to 5 supply current 5 additional per input pin; CC supply current other pins 4 5 input I capacitance C output O capacitance 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see ...

Page 7

... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions For type 74AHCT86 t propagation nA nY; see pd delay power pF dissipation V = GND capacitance [1] Typical values are measured at nominal supply voltage (V [ the same as t and PLH PHL [ used to determine the dynamic power dissipation (P ...

Page 8

... NXP Semiconductors PULSE GENERATOR Test data is given in Table 9. Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistor Test selection switch Fig 7. Load circuitry for switching times Table 9. Test data Type Input ...

Page 9

... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 11

... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 12

... Product data sheet Data sheet status Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN14 package added. Section 7: derating values added for DHVQFN14 package ...

Page 13

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 14

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Revision history ...

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