tp5335 Supertex, Inc., tp5335 Datasheet
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tp5335
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tp5335 Summary of contents
Page 1
... Distance of 1.6mm from case for 10 seconds. P-Channel Enhancement-Mode Vertical DMOS FET General Description The Supertex TP5335 is a low threshold enhancement- mode (normally-off) transistor utilizing an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coeffi ...
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... 1MHz -25V -150mA 25Ω, GEN PULSE GENERATOR R GEN INPUT TP5335 I † DRM (mA) (mA) -85 -400 = -100µ -1.0mA D = -1.0mA 125 -330V DS = -25V DS = -25V DS = -150mA D = -200mA ...
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... MAX 1.12 0.10 JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999. Drawings not to scale. (The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TP5335 A102607 ...