isppac-powr1208 Lattice Semiconductor Corp., isppac-powr1208 Datasheet - Page 4

• Manufacturer Part Number: isppac-powr1208
• Description: In-system Programmable Power Supply Sequencing Controller And Monitor
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Pin Descriptions (Continued)
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses above those listed values may cause permanent
damage to the device. Functional operation of the device at these or any other conditions above those indicated in
the operating sections of this specification is not implied.
1. IN1...IN4 are digital inputs to the PLD. The thresholds for these pins are referenced by the voltage on V
2. The 18 open-drain outputs can be powered independently of V
3. The four FET driver outputs (when this mode is activated, the corresponding 4 open-drain outputs are disabled) are internally powered and
4. V
5. The 12 VMON inputs can be biased independently of V
6. CLK is the PLD clock output in master mode. It is re-routed as an input in slave mode. The clock mode is set in software during design time.
7. RESET is an active low INPUT pin, external pull-up resistor to V
8. The CREF pin requires a 0.1µF capacitor to ground, near the device pin. This reference is used internally by the device. No additional exter-
V
V
HVOUTmax HVOUT pin voltage, max = V
V
VMON
V
T
T
T
1. V
2. Digital inputs are tolerant up to 5.5V, independent of the V
Number
A
S
SOL
DD
DDINP
IN
TRI
Symbol
ground). Exception, CLK pin 26 can only be pulled as high as V
can source up to 7.5V above V
In output mode it is an open-drain type pin and requires an external pull-up resistor (pull-up voltage must be ≤ V
POWR1208 devices can be tied together with one acting as the master, the master can use the internal clock and the slave can be clocked
by the master. The slave needs to be set up using the clock as an input.
one, and may turn “ON” or “OFF” the output pins, including the HVOUT pins depending on the polarity configuration of the outputs in the
PLD. If a reset function is needed for the other devices on the board, the PLD inputs and outputs can be used to generate these signals.
The RESET connected to the POR pin can be used if multiple ispPAC-POWR1208 devices are cascaded together in expansion mode or if
a manual reset button is needed to reset the PLD logic to the initial state. While using the ispPAC-POWR1208 in hot-swap applications it is
recommended that either the RESET pin be connected to the POR pin, or connect a capacitor to ground (such that the time constant is 10
ms with the pull-up resistor) from the RESET pin.
nal circuitry should be connected to this pin.
supply voltage for the given input logic range.
2
39
40
41
42
43
44
DDINP
DDINP
1
can be chosen independent of V
is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V
CREF
VMON8
VMON9
VMON10
VMON11
VMON12
Core supply voltage at pin
Digital input supply voltage for IN1-IN4
Input voltage applied, digital inputs
Input voltage applied, V
Tristated or open drain output, external voltage applied (CLK
pin 26 pullup ≤ V
Storage temperature
Ambient temperature with power applied
Maximum soldering temperature (10 sec. at 1/16 in.)
Name
Reference
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
DD
DD
.
Pin Type
).
MON
DD.
Parameter
It applies only to the four logic inputs IN1-IN4.
voltage monitor inputs
DD
+ 9V
1.17V
0V-5.72V
0V-5.72V
0V-5.72V
0V-5.72V
0V-5.72V
DD
Voltage Range
. The 12 VMON inputs can be as high as 7.0V Max (referenced to ground).
DDINP
8
DD,
DD
DD
voltage.
5
5
5
5
5
.
1-4
the open-drain outputs can be pulled up as high as +6.0V (referenced to
is required. When driven low it resets all internal PLD flip-flops to zero or
Reference for Internal Use, Decoupling Capacitor
(.1uf Required, CREF to GND)
Voltage Monitor Input 8
Voltage Monitor Input 9
Voltage Monitor Input 10
Voltage Monitor Input 11
Voltage Monitor Input 12
Conditions
ispPAC-POWR1208 Data Sheet
—
—
—
—
—
—
—
—
—
Description
DDINP
Min.
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-65
-55
—
.
DD
DDINP
). Multiple ispPAC-
Max.
pin with appropriate
150
125
260
6.0
6.0
6.0
7.0
6.0
15
Units
°C
°C
°C
V
V
V
V
V
V