xrt75r12 Exar Corporation, xrt75r12 Datasheet - Page 72

no-image

xrt75r12

Manufacturer Part Number
xrt75r12
Description
Twelve Channel E3/ds3/sts-1 Line Interface Unit With Jitter
Manufacturer
Exar Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
xrt75r12DIB
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
xrt75r12DIB-L
Manufacturer:
MURATA
Quantity:
460 000
Part Number:
xrt75r12DIB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
xrt75r12IB
Manufacturer:
EXAR
Quantity:
150
Part Number:
xrt75r12IB
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
xrt75r12IB
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Part Number:
xrt75r12IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
Company:
Part Number:
xrt75r12IB-L
Quantity:
2 021
XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
B
Reserved
IT
B
N
IT
UMBER
7
6
7
T
Loss of PRBS
Loss of PRBS Pat-
ABLE
Pattern Sync
T
ABLE
B
R/O
Reserved
tern Lock
IT
33: XRT75R12 R
N
6
AME
34: A
LARM
Digital LOS
Declared
Defect
B
R/O
IT
S
T
R/O
5
YPE
TATUS
EGISTER
Loss of PRBS Pattern Lock Indicator:
This READ-ONLY bit-field indicates whether or not the PRBS Receiver
(within the Receive Section of Channel n) is declaring PRBS Lock within the
incoming PRBS pattern.
If the PRBS Receiver detects a very large number of bit-errors within its
incoming data-stream, then it will declare the Loss of PRBS Lock Condition.
Conversely, if the PRBS Receiver were to detect its pre-determined PRBS
pattern with the incoming DS3, E3 or STS-1 data-stream, (with little or no bit
errors) then the PRBS Receiver will clear the Loss of PRBS Lock condition.
0 - Indicates that the PRBS Receiver is currently declaring the PRBS Lock
condition within the incoming DS3, E3 or STS-1 data-stream.
1 - Indicates that the PRBS Receiver is currently declaring the Loss of
PRBS Lock condition within the incoming DS3, E3 or STs-1 data-stream.
N
Analog LOS
(n = [0:11] &
R
OTE
Declared
b. The PRBS Receiver is enabled.
EGISTER
a. The PRBS Generator block (within the Transmit Section of the Chip is
c. The PRBS Pattern (that is generated by the PRBS Generator) is
Defect
B
R/O
: This register bit is only valid if all of the following are true.
MAP
enabled).
somehow looped back into the Receive Path (via the Line-Side) and
in-turn routed to the receive input of the PRBS Receiver.
IT
4
SHOWING
- C
69
M
HANNEL
= 0-5 & 8-D)
(FIFO Limit)
Declared
Alarm
B
R/O
FL
IT
A
3
LARM
n A
DDRESS
S
Receive LOL
D
TATUS
ESCRIPTION
Declared
Defect
B
R/O
IT
L
2
OCATION
R
EGISTERS
Receive LOS
Declared
= 0
Defect
B
R/O
IT
(AS_n)
XM
1
3
Condition
Transmit
REV. 1.0.4
B
DMO
R/O
IT
0

Related parts for xrt75r12