ICS9110 Integrated Circuit System, ICS9110 Datasheet - Page 4

• Manufacturer Part Number: ICS9110
• Manufacturer: Integrated Circuit System

AV9110
The AV9110 is programmed to generate clock frequencies by
entering data through the shift register. Figure 1 displays the
proper timing sequence. On the negative going edge of CE#,
the shift register is enabled and the data at the DATA pin is
loaded into the shift register on the rising edge of the SCLK.
Bit D0 is loaded first, followed by D1, D2, etc. This data
consists of the 24 bits shown in the Shift Register Bit
Assignment in Table 1, and therefore takes 24 clock cycles to
load. An internal counter then disables the input and transfers
Serial Programming
B
0 2
2 2
0 1
2 1
3 1
4 1
5 1
6 1
7 1
8 1
9 1
1 2
3 2
1 1
0
2
4
5
6
7
9
I
1
3
8
T
O
O
V
V
V
V
V
V
V
R
R
R
R
R
R
R
V
C
C
V
V
R
R
R
f e
f e
f e
f e
f e
f e
f e
L
L
s e
f e
s e
C
C
C
C
C
C
C
C
C
C
t u
u
p t
K
K
O
O
O
O
O
O
O
O
O
O
r e
r e
r e
r e
r e
r e
r e
r e
l p
r e
r e
X /
X /
t u
n e
n e
n e
n e
n e
n e
n e
n e
t u
e v
e v
f
f
f
f
f
f
f
p
u o
u o
e r
e r
e r
e r
e r
e r
e r
e r
n e
e c
e c
e c
e c
e c
e c
e c
e c
. d
. d
u o
u o
n e
p t
p t
u q
u q
u q
u q
u q
u q
u q
s -
b a
t u
t u
p t
p t
b a
S
S
f
f
f
f
f
f
f
c
a c
n e
n e
n e
n e
n e
n e
n e
e r
e r
e r
e r
e r
e r
e r
h
o l
h
e l
t u
t u
e l
e l
d
d
u o
u o
y c
y c
y c
y c
y c
y c
y c
u q
u q
u q
u q
u q
u q
u q
k c
i v i
i v i
C
d
d
C
d
d l
d l
n e
n e
n e
n e
n e
n e
n e
i v i
i v i
L
d
d
d
d
d
d
d
e d
e d
i v i
e s
L
v i
v i
v i
v i
v i
v i
i v i
K
e b
e b
y c
y c
y c
y c
y c
y c
y c
K
e d
e d
e l
e d
d i
d i
d i
d i
d i
d i
X /
V
V
e d
t c
0 (
d
d
d
d
d
d
d
r p
r p
r e
r e
r e
r e
r e
r e
O
O
C
C
0 (
( r
v i
v i
v i
v i
v i
v i
i v i
0 (
t =
D
D
n o
g o
g o
O
O
L (
A
d i
d i
d i
d i
d i
d i
=
M
t =
e d
0
1
s i r
D
D
a r
a r
d
S
r e
r e
r e
r e
r e
r e
C
S
i v i
s (
s (
s i r
S
0
1
I S
( r
t a t
m
m
) B
L
) B
e e
e e
L (
s (
s (
t a t
e d
m
K
m
G
M
) e
e e
e e
S
N
m
d e
T
T
S
) e
1 (
) B
y b
b a
b a
M
) B
d e
T
T
i h
=
b a
b a
e l
e l
E
, 1
i h
h g
r
N
e l
e l
f e
) 3
) 3
1
h g
T
=
r e
(
) 2
) 2
) 1
d
(
n e
i v i
) 1
e c
e d
r f
y b
q e
e u
8
c n
) y
the data to internal latches on the rising edge of the 24th
cycle of the SCLK. Any data entered after the 24th cycle is
ignored until CE# must remain low for a minimum of 24 SLCK
clock cycles. If CE# is taken high before 24 clock cycles have
elapsed, the data is ignored (no frequency change occurs)
and the counter is reset. Tables 1 and 2 display the bit location
for generating the output clock frequency and the output
divider circuitry, respectively.
E
V
Q
A
V
I
I
R
U
t n
t n
X
R
A
I
M
N
g e
g e
A
T
B
r e
r e
I
O
L
N
E
-
1 0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D
E
F
A
U
L
T
-
2 0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B
0 1
2 1
0 2
1 2
2 2
3 2
1 1
3 1
4 1
5 1
6 1
7 1
8 1
9 1
0
2
3
4
5
6
7
8
9
I
1
T