pt7a4401c Pericom Technology Inc, pt7a4401c Datasheet
pt7a4401c
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pt7a4401c Summary of contents
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... It generates the ST-BUS clock and framing sig- nals that are phase-locked to input reference signals of either 2.048MHz, 1.544MHz or 8kHz. The PT7A4401C is compliant with AT&T TR62411 Stratum 4 and Stratum 4 Enhanced, and ETSI ETS 300 011. It meets the requirements for jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, cap- ture range and phase slope, etc ...
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... Overall Operation ...................................................................................................................... 6 States of Operation .................................................................................................................... 7 Applications Information ........................................................................................................... 8 Detailed Specifications ...................................................................................................................... 10 Definition of Critical Performance Specifications .................................................................... 10 Absolute Maximum Ratings .................................................................................................... 11 Recommended Operating Conditions ...................................................................................... 11 DC Electrical and Power Supply Characteristics ..................................................................... 12 AC Electrical Characteristics ................................................................................................... 13 Mechanical Specifications ....................................................................................................... 25 Ordering Information ........................................................................................................................ 26 Notes ................................................................................................................................................. 27 PT0108(09/02) PT7A4401C T1/E1 System Synchronizer Contents 2 Data Sheet Page Ver:0 ...
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... Block Diagram Figure 1. Block Digram Phase REF Detector Input Impairment Monitor OSCi Master Clock OSCo PT0108(09/02) PT7A4401C T1/E1 System Synchronizer V GND CC Limiter & DCO1 Loop Filter State DCO2 Machine Feedback Frequency Select MUX RST MS FS1 FS2 3 Data Sheet Output Circuit C1 ...
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... Pin Configuration Figure 2. Pin Configuration OSCo OSCi C1.5 PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Referring to the block diagram on Page 3, the detailed func- tions of the PT7A4401C are described as follows. Master Clock As its master clock, the PT7A4401C uses either an external clock source or an external crystal and a few discrete compo- nents with its internal oscillator. Major Digital Phase-Locked Loop (DPLL) Block The major DPLL blocks are the Phase Detector, Limiter, Loop Filter, and Digitally Controlled Oscillators (DCO1 and DCO2) ...
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... H z Normal State Normal State, the output signals of the PT7A4401C are synchronized with the input reference signal by the DPLL Free-Run State Typically, the Free-Run State is used immediately following system power-up before network synchronization is achieved, or when a master clock is otherwise required ...
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... Clock Oscillator If using an external clock source, its output pin should be connected directly (not AC coupled) to the OSCi pin of the PT7A4401C, and the OSCo pin can be left open as shown in Figure 3 or connected as an output pin. Figure 3. Clock Oscillator Connection PT7A4401C ...
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... The reset time is not critical but should be greater than 300ns. Figure 5. Power-up Reset Circuit PT7A4401C 10k RST PT0108(09/02) PT7A4401C T1/E1 System Synchronizer Power Supply Decoupling The PT7A4401C has two V is used for protec- decoupling capacitors should be included as shown in Figure P 6. Figure 6. Power Supply Decoupling + 10nF 9 Data Sheet pins and two GND pins ...
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... Oscillators and is equal to 230ppm minus the accuracy of the master clock (OSCi). For example, a 32ppm master clock re- sults in a Lock Range of 198ppm. Capture Range: If the PT7A4401C DPLL is not at present in a state of synchronization (lock) with the incoming reference signal able to initiate (acquire) lock only if the signal’s frequency is within a certain range, called the Capture Range ...
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... Note: o Typical figures are and are for design aid only; not production tested. PT0108(09/02) PT7A4401C T1/E1 System Synchronizer Note +150 C Stresses greater than those listed under MAXIMUM +85 C RATINGS may cause permanent damage to the Only) ...
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... Note 5V (Freerun), FS1 = V , FS2 = GND, REF = GND, other inputs connected to GND All outputs are unloaded except for V PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Refer to the Test Conditions on Page 24 for details. PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Figure 7. Voltage Levels for Timing Parameter Measurement Signal PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Typical figures are and are for design aid only; not production tested. 2. The maximum and minimum timing is measured under recommended temperature conditions and power supplies. 3. TTL voltage levels are used for timing parameter measurement. PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... C and are for design aid only; not production tested. 2. The maximum and minimum timing is measured under recommended temperature conditions and power supplies. 3. TTL voltage levels are used for timing parameter measurement. Figure 8. Setup and Hold Timing of Input Controls F8 MS PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Figure 9. Timing Information for PT7A4401C RE F 8kH 1.544M 2.048M Hz F8 Note: Input to output delay values are valid after a RST with no further state changes. Figure 10. Output Timing PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Refer to the Test Conditions on Page 24 for details. PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Refer to the Test Conditions on Page 24 for details. PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Refer to the Test Conditions on Page 24 for details. PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Refer to the Test Conditions on Page 24 for details. PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Refer to the Test Conditions on Page 24 for details. PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Refer to the Test Conditions on Page 24 for details. PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... For capture range of ±130ppm. 19. 25pF capacitive load. 20. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI p-p where 1UI p-p = 1/20MHz. PT0108(09/02) PT7A4401C T1/E1 System Synchronizer 21. Jitter on reference input is less than 7ns p-p. 22. Applied jitter is sinusoidal. 23. Minimum applied input jitter magnitude to regain syn- chronization. 24. Loss of synchronization is obtained at slightly higher in- put jitter amplitudes ...
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... Mechanical Specifications Figure 11. 28-pin PLCC PT0108(09/02) PT7A4401C T1/E1 System Synchronizer 25 Data Sheet Ver:0 ...
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... PT0108(09/02) PT7A4401C T1/E1 System Synchronizer ...
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... Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0108(09/02) PT7A4401C T1/E1 System Synchronizer Notes Pericom Technology Inc. Web-Site: www.pti.com.cn, www.pti-ic.com ...