71m6534h-igt Maxim Integrated Products, Inc., 71m6534h-igt Datasheet - Page 26

• Manufacturer Part Number: 71m6534h-igt
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

71M6533/71M6534 Data Sheet
1.3.5 Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set
and of the associated op-codes is contained in the 71M653X Software User’s Guide (SUG).
1.3.6 UARTs
The 71M6533 and 71M6534 include a UART (UART0) that can be programmed to communicate with a
variety of AMR modules and other external devices. A second UART (UART1) is connected to the optical
port, as described in the
The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host proces-
sor at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins
is as follows:
The 71M6533 and 71M6534 have several UART-related registers for the control and buffering of serial
data.
The serial buffers consist of sets of two separate registers (one set for each UART), a transmit buffer
(S0BUF, S1BUF) and a receive buffer (R0BUF, R1BUF). Writing data to the transmit buffer starts the
26
IFLAGS
INTBITS
(INT0 … INT6)
(Alternate
UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are
input LSB first.
UART0 TX: This pin is used to output the serial data. The bytes are output LSB first.
Register
Name)
0xE8[0]
0xE8[1]
0xE8[2]
0xE8[3]
0xE8[4]
0xE8[5]
0xE8[6]
0xE8[7]
0xF8[6:0]
0xF8[7]
Address
SFR
1.4.6 UART and
© 2007-2009 TERIDIAN Semiconductor Corporation
Only byte operations on the entire INTBITS register should be used when
writing. The byte must have all bits set except the bits that are to be cleared.
IE_XFER
IE_RTC
FW_COL0
FW_COL1
IE_PB
IE_WAKE
PLL_RISE
PLL_FALL
INT6 … INT0
WD_RST
Bit Field
Name
Optical Interface section.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
Description
This flag monitors the XFER_BUSY interrupt. It
is set by hardware and must be cleared by the
interrupt handler.
This flag monitors the RTC_1SEC interrupt. It
is set by hardware and must be cleared by the
interrupt handler.
This flag indicates that a flash write was at-
tempted while the CE was busy.
This flag indicates that a flash write was in pro-
gress when the CE was attempting to begin a
code pass.
This flag indicates that the wake-up pushbutton
was pressed.
This flag indicates that the MPU was awakened
by the autowake timer.
PLL_RISE Interrupt Flag:
Write 0 to clear the PLL_RISE interrupt flag.
PLL_FALL Interrupt Flag:
Write 0 to clear the PLL_FALL interrupt flag.
Interrupt inputs. The MPU may read these bits
to see the status of external interrupts INT0 up
to INT6. These bits do not have any memory
and are primarily intended for debug use.
The WDT is reset when a 1 is written to this bit.
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