xr16c2552ij Exar Corporation, xr16c2552ij Datasheet - Page 18

• Manufacturer Part Number: xr16c2552ij
• Description: 2.97v To 5.5v Dual Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

XR16C2552
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
IER[3]: Modem Status Interrupt Enable
IER[7:4]: Reserved
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 8, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
]
ISR[0]: Interrupt Status
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 8).
ISR[5:4]: Reserved
4.5
4.5.1
4.5.2
P
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
L
RIORITY
EVEL
1
2
3
4
5
-
Interrupt Status Register (ISR) - Read-Only
Interrupt Generation:
Interrupt Clearing:
B
IT
0
1
0
0
0
0
-3
ISR R
B
EGISTER
IT
1
1
1
0
0
0
-2
S
B
T
TATUS
IT
1
0
0
1
0
0
ABLE
-1
B
8: I
ITS
B
NTERRUPT
IT
0
0
0
0
0
1
-0
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
None (default)
S
OURCE AND
18
P
RIORITY
S
OURCE OF
L
EVEL
I
NTERRUPT
xr
REV. 1.0.0