xr16l2752ij Exar Corporation, xr16l2752ij Datasheet - Page 8

• Manufacturer Part Number: xr16l2752ij
• Description: 2.25v To 5.5v Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
Each UART channel in the 2752 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM), and a user accessible Scratchpad Register (SPR).
Beyond the general 16C2550 features and capabilities, the 2752 offers enhanced feature registers (AFR,
EMSR, FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware
flow control, Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable,
FIFO trigger level control, FIFO level counters, and simultaneous writes to both channels. All the register
functions are discussed in full detail later in
During a write mode cycle, the setting of Alternate Function Register (AFR) bit-0 to a logic 1 will override the
CHSEL selection and allows a simultaneous write to both UART channel sections. This functional capability
allow the registers in both UART channels to be modified concurrently, saving individual channel initialization
time. Caution should be considered, however, when using this capability. Any in-process serial data transfer
may be disrupted by changing an active channel’s mode.
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B (MF# A/B becomes RXRDY# A/B output when AFR[2:1] = ‘10’) and TXRDY# A/B output
pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode
operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for
more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1).
When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR bit-3 = 0), the 2752 is
placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-
3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block
sequence determined by the programmed trigger level. In this mode, the 2752 sets the TXRDY# pin when the
transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO becomes empty. The following
table shows their behavior. Also see
2.6
2.7
2.8
RXRDY# A/B LOW = 1 byte.
TXRDY# A/B LOW = THR empty.
P
INS
Channel A and B Internal Registers
Simultaneous Write to Channel A and B
DMA Mode
HIGH = no data.
HIGH = byte in THR.
(FIFO D
FCR
T
ABLE
BIT
ISABLED
-0=0
2: TXRDY#
)
CS#
1
0
0
LOW = at least 1 byte in FIFO.
HIGH = FIFO empty.
LOW = FIFO empty.
HIGH = at least 1 byte in FIFO.
Figures 18
T
ABLE
(DMA Mode Disabled)
AND
CHSEL
“Section 3.0, UART INTERNAL REGISTERS” on page
FCR Bit-3 = 0
1: C
RXRDY# O
X
1
0
through 23.
HANNEL
8
A
UTPUTS IN
AND
Channel A selected
Channel B selected
FCR B
UART de-selected
F
B S
UNCTION
IT
HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs.
LOW to HIGH transition when FIFO empties.
LOW = FIFO has at least 1 empty location.
HIGH = FIFO is full.
-0=1 (FIFO E
FIFO
ELECT
AND
DMA M
(DMA Mode Enabled)
NABLED
FCR Bit-3 = 1
ODE
)
xr
20.
REV. 1.2.1