xr16v554 Exar Corporation, xr16v554 Datasheet - Page 20

• Manufacturer Part Number: xr16v554
• Description: 2.25v To 3.6v Quad Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

XR16V554/554D
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
SEE”RECEIVER” ON PAGE 24.
SEE”TRANSMITTER” ON PAGE 22.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
N
MCR
RHR
MSR
DLM
THR
FCR
LCR
SPR
R
LSR
DLL
IER
ISR
AME
EG
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
R
W
WR
WR
RD
RD
EAD
RITE
/
RX FIFO
Enabled
Trigger
Enable
Global
FIFOs
B
FIFO
Error
Input
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
CD#
RX
IT
0
0
-7
T
ABLE
RI# Input
RX FIFO
Enabled
Trigger
Set TX
THR &
Empty
FIFOs
Break
B
Bit-6
Bit-6
TSR
Bit-6
Bit-6
Bit-6
IT
0
0
8: I
-6
16C550 Compatible Registers
Baud Rate Generator Divisor
NTERNAL
Empty
Parity
DSR#
B
Input
Bit-5
Bit-5
THR
Bit-5
Bit-5
Bit-5
Set
IT
0
0
0
0
-5
R
20
EGISTERS
RX Break
Lopback
Internal
Enable
Parity
CTS#
B
Even
Input
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
IT
0
0
0
-4
D
Stat. Int.
Framing
Modem
Source
(OP2#)
ESCRIPTION
Enable
Enable
Enable
Enable
Output
Mode
Parity
B
Delta
DMA
Error
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
INT
INT
RX
IT
-3
RX Line
(OP1#)
Enable
Source
Reset
Parity
B
FIFO
Rsvd
Error
Delta
Bit-2
Bit-2
Stat.
Bit-2
Stop
Bit-2
Bit-2
Bit-2
INT
Bits
RI#
Int.
TX
RX
IT
-2
Control
Enable
Source
Length
Output
Empty
DSR#
Reset
RTS#
Over-
Word
B
FIFO
Error
Delta
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
run
TX
RX
RX
Int
IT
-1
Control
Enable
Source
Enable
Length
Output
FIFOs
Ready
DTR#
CTS#
Word
B
Delta
Data
Data
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
INT
RX
Int.
RX
IT
-0
LCR[7] = 0
LCR[7] = 0
LCR≠0xBF
C
LCR[7]=1
REV. 1.0.2
OMMENT