xr16v2650im Exar Corporation, xr16v2650im Datasheet - Page 30
![no-image](/images/manufacturer_photos/0/2/243/exar_corporation_sml.jpg)
xr16v2650im
Manufacturer Part Number
xr16v2650im
Description
High Performance Duart With 32-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16V2650IM.pdf
(47 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
xr16v2650im-F
Manufacturer:
Exar Corporation
Quantity:
10 000
XR16V2650
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
MCR[5]: Xon-Any Enable (requires EFR bit-4=1)
•
•
MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4=1)
•
•
MCR[7]: Clock Prescaler Select (requires EFR bit-4=1)
•
•
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
•
•
LSR[1]: Receiver Overrun Error Flag
•
•
LSR[2]: Receive Data Parity Error Tag
•
•
LSR[3]: Receive Data Framing Error Tag
•
•
LSR[4]: Receive Break Error Tag
•
•
4.8
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the V2650 is programmed to use the Xon/Xoff flow control.
Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX output will be idling LOW.
PAGE 18.
Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO.
Line Status Register (LSR) - Read Only
To change the polarity of the IrDA data at the Rx input, see MCR[2].
30
SEE”INFRARED MODE” ON
REV. 1.0.2