xr16v2552il32 Exar Corporation, xr16v2552il32 Datasheet - Page 7

• Manufacturer Part Number: xr16v2552il32
• Description: High Performance Duart With 16-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2552 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in
The V2552 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the V2552 is
operating at 2.5V, its V
transceiver that is operating at 5V.
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see
function in the device.
The XR16V2552 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DVID will
provide 0x02 for the XR16V2552 and reading the content of DREV will provide the revision of the part; for
example, a reading of 0x01 means revision A.
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select
the UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure,
F
2.0 FUNCTIONAL DESCRIPTIONS
2.1
2.2
2.3
2.4
2.5
IGURE
3. XR16V2552 D
CPU Interface
5-Volt Tolerant Inputs
Device Reset
Device Identification and Revision
Channel A and B Selection
UART_CHSEL
UART_RESET
Table
UART_CS#
UART_INTA
UART_INTB
(RXRDYA#)
(RXRDYB#)
TXRDYA#
TXRDYB#
IOW#
IOR#
when AFR[2:1] = '00'. MF# A/B becomes BAUDOUT# A/B when AFR[1:0] = '01'.
Pins in parentheses become available through the MF# pin. MF# A/B becomes RXRDY# A/B when AFR[2:1] = '10'. MF# A/B becomes OP2# A/B
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
15). An active high pulse of longer than 40 ns duration will be required to activate the reset
OH
ATA
may not be high enough to meet the requirements of the V
B
US
I
NTERCONNECTIONS
IOR#
IOW#
CHSEL
TXRDYA#
TXRDYB#
CS#
INTA
INTB
(RXRDYA#)
(RXRDYB#)
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
RESET
7
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
Channel A
Channel B
UART
UART
(BAUDOUTA#)
(BAUDOUTB#)
(OP2A#)
(OP2B#)
DTRA#
RTSA#
CTSA#
DSRA#
DSRB#
DTRB#
RTSB#
CTSB#
CDA#
CDB#
GND
RIA#
VCC
RIB#
TXA
RXA
TXB
RXB
VCC
Serial Interface of
Serial Interface of
RS-232, RS-422
RS-232, RS-422
Figure 3
IH
of a CPU or a serial
XR16V2552