74VHC08MX Fairchild Semiconductor, 74VHC08MX Datasheet - Page 8

• Manufacturer Part Number: 74VHC08MX
• Description: IC GATE AND QUAD 2IN 14-SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74VHCr

Specifications of 74VHC08MX

• Logic Type: AND Gate
• Number Of Inputs: 2
• Number Of Circuits: 4
• Current - Output High, Low: 8mA, 8mA
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Logic Family: VHC
• Logical Function: AND
• Number Of Elements: 4
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 12ns
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC N
• Number Of Outputs: 1
• Technology: CMOS
• Mounting: Surface Mount
• Pin Count: 14
• Operating Temperature Classification: Industrial
• Quiescent Current: 2uA
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74VHC08MX; 74VHC08MXTR

©1992 Fairchild Semiconductor Corporation
74VHC08 Rev. 1.4.0
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
A. CONFORMS TO JEDEC REGISTRATION MO-153,
B. DIMENSIONS ARE IN MILLIMETERS
E. LANDPATTERN STANDARD: SOP65P640X110-14M
D. DIMENSIONING AND TOLERANCES PER ANSI
F. DRAWING FILE NAME: MTC14REV6
AND TIE BAR EXTRUSIONS
VARIATION AB, REF NOTE 6
Y14.5M, 1982
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
0.43 TYP
(Continued)
8
0.65
R0.09 min
0.45
1.65
1.00
R0.09min
12.00°
TOP & BOTTOM
6.10
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