xr16m2550 Exar Corporation, xr16m2550 Datasheet - Page 33

• Manufacturer Part Number: xr16m2550
• Description: High Performance Low Voltage Duart With 16-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00 (DLD = 0xXX).
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, and DLD
to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.
This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it
is recommended to leave it enabled, logic 1.
•
•
4.13
4.14
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-
7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5,
MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR
C
ONT
X
X
X
0
0
1
0
1
1
0
1
0
Device Revision Register (DREV) - Read Only
BIT
Enhanced Feature Register (EFR)
-3
-3
EFR
C
ONT
X
X
X
0
0
0
1
1
0
1
1
0
BIT
-2
-2
T
ABLE
EFR
C
ONT
HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO
14: S
X
X
X
X
0
0
1
0
1
1
1
1
BIT
-1
-1
OFTWARE
Table
EFR
C
ONT
14). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
0
X
X
X
X
0
0
1
1
1
1
1
F
BIT
33
LOW
-0
-0
C
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1, Xoff1
Transmit Xon2, Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1, Xoff1
Receiver compares Xon2, Xoff2
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
ONTROL
T
RANSMIT AND
F
UNCTIONS
R
ECEIVE
S
OFTWARE
XR16M2550
F
LOW
C
ONTROL