xr16m2751 Exar Corporation, xr16m2751 Datasheet - Page 27

• Manufacturer Part Number: xr16m2751
• Description: High Performance Duart With 64-byte Fifo And Powersave
• Manufacturer: Exar Corporation

REV. 1.0.0
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ISR[0]: Interrupt Status
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ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
Table
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. If it is a special
character interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is
received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has been de-
asserted.
4.4.2
P
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
Special character interrupt is cleared by a read to ISR or after the next character is received.
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
Wake-up Indicator is cleared by a read to the ISR register.
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition) or the device has come out of sleep mode.
L
RIORITY
EVEL
1
2
3
4
5
6
7
-
10).
Interrupt Clearing:
B
IT
0
0
0
0
0
0
1
0
-5
B
IT
0
0
0
0
0
1
0
0
-4
ISR R
B
T
EGISTER
IT
0
1
0
0
0
0
0
0
ABLE
-3
10: I
B
S
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
IT
TATUS
1
1
1
0
0
0
0
0
-2
NTERRUPT
B
B
ITS
IT
1
0
0
1
0
0
0
0
-1
S
OURCE AND
27
B
IT
0
0
0
0
0
0
0
1
-0
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
RXRDY (Received Xoff or Special character)
CTS#, RTS# change of state
None (default) or Wake-up Indicator
P
RIORITY
L
EVEL
S
OURCE OF INTERRUPT
XR16M2751