xr16m570 Exar Corporation, xr16m570 Datasheet
xr16m570
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xr16m570 Summary of contents
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... An internal loopback capability allows onboard diagnostics. The M570 is available in 24-pin QFN, 32-pin QFN and 25-pin BGA packages. All three packages offer the 16 mode (Intel bus) interface only OTE 1 Covered by U.S. Patent #5,649,122 XR16M570 B D IGURE LOCK IAGRAM ave ...
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... QFN Corner CTS# VCC ORDERING INFORMATION P N ART UMBER XR16M570IL24 XR16M570IL32 XR16M570IB25 24- QFN, 32- QFN 25-BGA P PIN PIN AND DSR CD# 26 IOR GND VCC IOW# ...
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... EFR[6], MCR[1] and IER[6 UART Clear-to-Send (active low) or general purpose input. It can be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be connected to VCC when not used UART Data-Terminal-Ready (active low) or general purpose output. 3 XR16M570 D ESCRIPTION ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO Pin Description 24-QFN 32-QFN 25-BGA N AME DSR CD RI ANCILLARY SIGNALS XTAL1 8 10 XTAL2 - 11 PwrSave 7 - RESET 17 23 VCC 19 28 GND 10 13 GND Center Center Pad Pad 15, 16 Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. ...
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... FIFOs, Automatic RTS/CTS Hardware Flow Control, Automatic Xon/Xoff and Special Character Software Flow Control, infrared encoder and decoder (IrDA ver 1.0 and 1.1), programmable fractional baud rate generator with a prescaler of divide and data rate Mbps. The XR16M570 can operate from 1.62 to 3.63 volts. The M570 is fabricated with an advanced CMOS process. ...
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... The M570 data interface supports the Intel compatible types of CPUs. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# inputs. A typical data bus interconnection for Intel mode is shown XR16M570 T I IGURE YPICAL ...
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... Serial Interface The M570 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422 transceivers www.exar.com or send an e-mail to uarttechsupport@exar.com XR16M570 T S IGURE YPICAL ERIAL ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO F 5. XR16M570 T S IGURE YPICAL ERIAL DTR# UART NTERFACE ONNECTIONS VCC VCC RTS# DE VCC RE# NC CTS# DSR# CD GND RS-485 Half-Duplex Serial Interface ...
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... HIGH = FIFO below trigger level or FIFO empty 2: INT PERATION FOR ECEIVER ) FCR B ISABLED LOW = FIFO below trigger level HIGH = FIFO above trigger level or RX Data Timeout 9 XR16M570 Table 1 and 2 Figure 19 through 22 (FIFO NABLED - (FIFO NABLED ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 2.6 Crystal Oscillator or External Clock Input The M570 includes an on-chip oscillator to produce a clock for the baud rate generators in the device when a crystal is connected between XTAL1 and XTAL2 as show below. The CPU data bus does not require this clock for bus operation ...
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... Independent TX/RX BRG The XR16M570 has two independent sets of TX and RX baud rate generator. Please see the RX can work in different baud rate by setting DLD, DLL and DLM register. For example, TX can transmit data to the remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate setting, please See ” ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO IGURE AUD ATE ENERATOR Prescaler Divide by 1 Crystal XTAL1 Osc / XTAL2 Buffer Prescaler Divide ABLE YPICAL DATA RATES WITH A Required D 16x IVISOR FOR Output Data Clock O Rate (Decimal) ...
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... T O IGURE RANSMITTER PERATION IN NON Data Byte 16X Clock ( DLD[5:4] ) 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO -FIFO M ODE Transmit Holding Register THR Interrupt (ISR bit-1) (THR) Enabled by IER bit-1 M Transmit Shift Register (TSR XR16M570 TXNOFIFO1 ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 2.8.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the FIFO becomes empty ...
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... FIFO is Enabled bit-0=1 D ata fills to R TS# de-asserts w hen data fills above the flow 14 control trigger level to suspend rem ote transm itter. Enable by EFR bit-6= bit-1. R eceive D ata 15 XR16M570 Receive Data Characters RXFIFO1 M ODE R eceive D ata C haracters R X FIFO 1 ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 2.10 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features is enabled to fit specific application requirement (see • ...
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... RTSA# CTSB# TXA RXB CTSA# RTSB# ON OFF 7 ON OFF 8 Restart 6 Suspend 9 RTS High RTS Low 5 RX FIFO Threshold Threshold 17 XR16M570 Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level FIFO 12 Trigger Level RTSCTS1 ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 2.13 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M570 will halt transmission (TX) as soon as the current character has completed transmission ...
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... Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each time it senses a light pulse, it returns a logic 1 to the data bit stream. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO Figure 13 below. 19 XR16M570 Figure 13. ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO F 13 IGURE NFRARED RANSMIT ATA TX Data Transmit IR Pulse (TX Pin) Receive IR Pulse (RX pin) RX Data 2.17 Sleep Mode with Auto Wake-Up and Power-Save feature The M570 supports low voltage system designs, hence, a sleep mode with auto wake-up and power-save feature is included to reduce its power consumption when the chip is not actively used ...
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... The M570 has the wake up interrupt. By setting the FCR bit-3, wake up interrupt is enabled or disabled. The default status of wake up interrupt is disabled. Please Write-Only” on page 29. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO Figure 1 on page See ”Section 4.5, FIFO Control Register (FCR XR16M570 1) from other bus activities that ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 2.18 Internal Loopback The M570 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 14 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending ...
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... Write-only Read-only E R NHANCED EGISTERS Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 23 XR16M570 /W C RITE OMMENTS LCR[ LCR ≠ 0xBF, DLL = 0x00, DLM = 0x00 LCR[ LCR ≠ 0xBF See DLD[7:6] LCR[ LCR ≠ 0xBF, EFR[ LCR[ LCR[ EFR[ LCR ≠ 0xBF if EFR[ LCR ≠ ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO T 7: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/WR 0/ CTS# Int. Enable ISR RD FIFOs Enabled FCR WR RX FIFO Trigger ...
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... ISR [5:4], Flow FCR[5:3], Cntl MCR[7:5], Bit-3 DLD Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 25 XR16M570 EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 LCR[ LCR≠0xBF DLL= 0x00 ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M570 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... CTS# is when the remote transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control. • RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control. • Wakeup interrupt is generated when the M570 wakes up from the sleep mode. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 27 XR16M570 ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 4.4.2 Interrupt Clearing: • LSR interrupt is cleared by a read to the LSR register. • RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. • RXRDY Time-out interrupt is cleared by reading RHR. • ...
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... Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 21. Table 9 below shows the selections. Note that the Table 9 29 XR16M570 shows the complete selections. ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO ABLE RANSMIT AND FCR B -7 FCR B -6 FCR 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register ...
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... Logic 1 = Force DTR# output LOW. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO T 10: P ABLE ARITY SELECTION -4 LCR ARITY SELECTION parity 0 1 Odd parity 1 1 Even parity 0 1 Force parity to mark, HIGH 1 1 Forced parity to space, LOW 31 XR16M570 ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO MCR[1]: RTS# Output The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output. ...
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... Logic global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the RX FIFO. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 33 XR16M570 ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 4.9 Modem Status Register (MSR) - Read Only This register provides the current state of the modem interface input signals. Lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state ...
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... REV. 1.0.0 4.10 Modem Status Register (MSR) - Write Only This register provides the advanced features of XR16M570. Lower four bits of this register are reserved. Writing to the higher four bits enables additional functions. MSR[3:0]: Reserved MSR[4]: Enable/Disable Transmitter (Requires EFR[ • Logic 0 = Enable Transmitter (default). ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO EMSR[2]: Send TX Immediately • Logic not send TX immediately (default). • Logic 1 = Send TX immediately. When FIFO is enabled and this bit is set, the next data will be to the TX shift register. Thus, the data will be sent out immediately instead of queuing in the FIFO. Every time, only 1 byte will be send out ...
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... Transmitter and Receiver uses same BRG. Transmitter and Receiver uses different BRGs. Writing to DLL, DLM and DLD[5:0] configures the BRG for TX. Transmitter and Receiver uses different BRGs. Writing to DLL, DLM and DLD[5:0] configures the BRG for RX. Transmitter and Receiver uses same BRG. Table 12. 37 XR16M570 ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO FCTR[6]: Scratchpad Swap • Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode. • Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced Mode Select Register is selected when it is written into ...
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... These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. For more details, see Table 5. The xoff2 is also used as auto address detect register when the auto 9-bit mode enabled. See ”Section 2.15.1, Auto Address Detection” on page 19. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 39 XR16M570 ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REGISTERS DLM, DLL (Both TX and RX) DLD RHR THR IER FCR ISR LCR MCR LSR MSR SPR EMSR FC FCTR EFR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX RTS# DTR# INT T 16: UART RESET CONDITIONS ABLE RESET STATE DLM = 0x00 and DLL = 0x01 ...
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... IMITS IMITS 1.8V 2. -0.3 0.3 -0.3 0.4 1.4 VCC 2.0 VCC -0.3 0.2 -0.3 0.5 1.4 VCC 1.8 VCC 0.4 0.4 1.8 1.4 ±15 ±15 ±15 ± 1 XR16M570 3.6 Volts GND-0 3 - -65 to +150 C 500 C/W, theta- C C/W, theta- C C/W, theta-jc = 98.2 C/W L IMITS 3. NITS ONDITIONS -0.3 0.6 V 2.4 VCC V -0.3 0 ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO SEE”POWER-SAVE FEATURE” ON PAGE 21. M570 should NOT be lower than its VCC supply. AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER XTAL1 UART Crystal Frequency ECLK External Clock Frequency T External Clock Time Period ...
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... CLK OSC IMING XR16M570 L L IMITS IMITS 3.3V ± 10% U NIT ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO F 17 IGURE ODE NTEL ATA A0-A2 Valid Address T AS CS# IOR# T RDV D0- IGURE ODE NTEL ATA A0-A2 Valid Address T AS CS# IOW# D0- EAD IMING ...
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... Byte in RHR in RHR T T SSR SSR Active Active Data Data Ready Ready -FIFO M ] IMING ON ODE Stop D0:D7 Bit ISR is read T WRI T SRT XR16M570 D0:D7 T SSR 1 Byte in RHR T SSR Active Data Ready T RR RXNFM D0:D7 ISR is read T WRI T SRT T WT TXNonFIFO ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO F 21 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX S D0:D7 S D0:D7 Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading data out of RX FIFO & I IGURE RANSMIT EADY ...
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... INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.154 0.161 3.90 0.098 0.110 2.50 0.007 0.012 0.18 0.0197 BSC 0.50 BSC 0.014 0.018 0.35 0.008 - 0.20 47 XR16M570 Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm MAX 1.00 0.05 0.25 4.10 2.80 0.30 0.45 - ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.193 0.201 4.90 0.138 ...
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... TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO ) (A1 corner feature is mfger option INCHES MILLIMETERS MIN MAX MIN 0.028 0.031 0.70 0.005 0.007 0.13 0.022 0.024 0.57 0.114 0.122 2.90 0.079 BSC 0.008 0.012 0.20 0.020 BSC 49 XR16M570 1 A1 corner MAX 0.80 0.19 0.61 3.10 2.00 BSC 0.30 0.50 BSC ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REVISION HISTORY D R ATE EVISION September 2008 Rev 1.0.0 Final Datasheet. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement ...
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... PRODUCT DESCRIPTION ...................................................................................................................... 5 2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 6 2.1 CPU INTERFACE ................................................................................................................................................ XR16M570 IGURE YPICAL NTEL 2.2 SERIAL INTERFACE........................................................................................................................................... XR16M570 T S IGURE YPICAL ERIAL F 5. XR16M570 T S IGURE YPICAL ERIAL 2.3 DEVICE RESET ................................................................................................................................................... 9 2.4 INTERNAL REGISTERS...................................................................................................................................... 9 2.5 INT OUPUT .......................................................................................................................................................... INT ABLE IN PERATION FOR RANSMITTER T 2: INT P ...
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... XR16M570 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 27 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 27 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... FIFO T ABLE RANSMIT AND ECEIVE 4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 30 ...