ak4359 AKM Semiconductor, Inc., ak4359 Datasheet - Page 23

• Manufacturer Part Number: ak4359
• Description: 106db 192khz 24-bit 8ch Dac
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0289-E-02
(2) I
The AK4359 supports the fast-mode I
Figure 15 shows the data transfer sequence at the I
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 19). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction bit
(R/W) (Figure 16). The most significant six bits of the slave address are fixed as “001001”. The next one bit are CAD0
(device address bit). The bit identify the specific device on the bus. The hard-wired input pin (CAD0 pin) set them. If the
slave address match that of the AK4359 and R/W bit is “0”, the AK4359 generates the acknowledge and the write
operation is executed. If R/W bit is “1”, the AK4359 generates the not acknowledge since the AK4359 can be only a
slave-receiver. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during
the acknowledge clock pulse (Figure 20).
The second byte consists of the address for control registers of the AK4359. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 17). Those data after the second byte contain control data. The format is MSB
first, 8bits (Figure 18). The AK4359 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 19).
The AK4359 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4359 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits address
counter is incremented by one, and the next data is taken into next address automatically. If the addresses exceed 1FH
prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 21) except for the START and the STOP
condition.
2
C-bus Control Mode (I2C pin = “H”)
SDA
D7
0
0
S
T
A
R
T
S
Slave
Address
Figure 15. Data transfer sequence at the I
D6
(Those CAD1/0 should match with CAD1/0 pins)
0
0
Figure 18. Byte structure after the second byte
2
R/W
C-bus system (max: 400kHz).
A
C
K
Sub
Address(n)
D5
1
0
Figure 17. The second byte
Figure 16. The first byte
2
C-bus mode. All commands are preceded by a START condition. A
A
C
K
A4
D4
0
- 23 -
Data(n)
A3
D3
0
A
C
K
Data(n+1)
2
D2
A2
C-bus mode
1
A
C
K
CAD0
A1
D1
A
C
K
Data(n+x)
R/W
A0
D0
A
C
K
S
T
O
P
P
[AK4359]
2006/03