ak4342 AKM Semiconductor, Inc., ak4342 Datasheet - Page 27

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ak4342

Manufacturer Part Number
ak4342
Description
24-bit Stereo Dac With Hp-amp & 2v Line-out
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
PDN pin must keep “L” until all power supply pins (AVDD, DVDD, PVDD, HVDD and TVDD) are applied. After they
are applied, PDN pin must be set to “H”. After exiting reset (PDN pin: “L”
LAUX, RAUX, LOUT, ROUT and charge pump circuit) switch to the power-down state. The contents of the control
register are maintained until the reset is done.
DAC exits reset and power down state by MCLK edge after PMDAC bit is changed to “1”, and then DAC is powered up
and the internal timing starts clocking by LRCK edge. DAC is in power-down mode until MCLK and LRCK are input.
HPL/HPR pins
(
(1) After Power Up: PDN pin “L”
(2) DFS1-0, DIF2-0, DEM1-0, FS3-0, PTS1-0, STS1-0, PUT1-0, LRP, BCKP and DACLR bits should be set during this
(3) Supply the external clocks (MCLK, BICK, LRCK)
MS0506-E-02
Power Supply
PDN pin
PMVCM bit
Clock Input
PMCP bit
PVEE pin
DAC Internal
PMHP bit
(or PMLO bit)
PMDAC bit
HMUTEL/R bits
(or LMUTE bit)
or LOUT/ROUT pins)
LOUT/ROUT pins
(or HPL/HPR pins)
PMLO bit
(or PMHP bit)
LMUTE bit
(or HMUTEL/R bit)
State
System Reset
Power-Up/Down Sequence
period before the DAC and charge pump circuit are powered-up.
“L” time (1) of 150ns or more is needed to reset the AK4342.
PDN pin must keep “L” until all power supply pins (AVDD, DVDD, PVDD, HVDD and TVDD) are applied.
After they are applied, PDN pin must be set to “H”.
Power Down
Don’t care
0V
(1)
0V
(2)
(3)
(4)
(5)
Figure 20. Example of Power-up/down Sequence
MUTE
0V
“H”
(6)
(7)
Normal
MUTE
(8)
- 27 -
Normal Operation
MUTE
PVEE
(9)
(6)
(7)
“H”), all blocks (VCOM, DAC, HPL, HPR,
Normal
MUTE
(8)
0V
(9)
(10)
Don’t care
Power Down
0V
[AK4342]
0V
2006/07

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