ICS309 Integrated Circuit System, ICS309 Datasheet - Page 4

• Manufacturer Part Number: ICS309
• Manufacturer: Integrated Circuit System

MDS 309 A
Int egrat ed C ircuit Syst ems
AC Parameters for Writing to the ICS309
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a
commonly used trace impedance), place a 33 resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20 .
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS309 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
t
DA TA
SC LK
STRO BE
setup
Figure 2. Tim ing Diagram for Program m ing the IC S309
P r e l i m i n a r y I n f o r m a t i o n
Bit160
Parameter
t
SETUP
t
HOLD
t
t
Bit159
W
S
Bit158
t
h old
52 5 Race Str eet, San Jose, C A 9 5126
Hold time after SCLK
Strobe pulse width
SCLK Frequency
Bit3
Data wait time
Setup time
Condition
Bit2
4
Bit1
t
w
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device.
Crystal capacitors must be connected from each of the
pins X1 and X2 to ground. The value (in pF) of these
crystal caps should equal (C
C
crystal with a 16 pF load capacitance, each crystal
capacitor would be 20 pF [(16-6) x 2] = 20.
Optional on-chip capacitors may be programmed for
crystals with 18 pF load capacitance.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
L
= crystal load capacitance in pF. Example: For a
t
s
S
ERIAL
P
Min.
ROGRAMMABLE
10
10
10
40
tel ( 408) 295- 9800
Max.
L
30
-6pF)*2. In this equation,
T
RIPLE
w w w.i c s t .c o m
Units
Revision 053003
MHz
ns
ns
ns
ns
SS C
ICS309
LOCK