xrt83l30 Exar Corporation, xrt83l30 Datasheet - Page 65

• Manufacturer Part Number: xrt83l30
• Description: Xrt83l30 -single-channel T1/e1/j1 Long-haul, Short-haul Line Interface Unit
• Manufacturer: Exar Corporation

REV. 1.0.1
R
EGISTER
10001
B
D7
D6
D5
D4
IT
A
#
DDRESS
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
CLKSEL2
CLKSEL1
CLKSEL0
Reserved
N
AME
T
ABLE
35: M
Clock Select Inputs for Master Clock Synthesizer bit 2 : In
Host mode, CLKSEL[2:0] are input signals to a programmable
frequency synthesizer that can be used to generate a master
clock from an external accurate clock source according to the fol-
lowing table:
In Hardware mode the state of these bits are ignored and the
master frequency PLL is controlled by the corresponding Hard-
ware pins.
Clock Select inputs for Master Clock Synthesizer bit 1: See
description of bit D6 for function of this bit.
Clock Select inputs for Master Clock Synthesizer bit 0: See
description of bit D6 for function of this bit.
MCLKE1
2048
2048
2048
1544
1544
2048
kHz
128
128
256
256
16
16
56
56
64
64
ICROPROCESSOR
8
8
M CLKT1
2048
1544
1544
1544
1544
2048
kHz
X
X
X
X
X
X
X
X
X
X
X
X
CLKSEL2
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
62
R
EGISTER
F
CLKSEL1
UNCTION
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
#17
CLKSEL0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BIT DESCRIPTION
MCLKRATE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLKOUT
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
kHz
R
EGISTER
T
XRT83L30
R/W
R/W
R/W
R/W
YPE
R
V
ALUE
ESET
0
0
0
0