tc59lm836dkb TOSHIBA Semiconductor CORPORATION, tc59lm836dkb Datasheet
![no-image](/images/manufacturer_photos/0/6/670/toshiba_semiconductor_corporation_sml.jpg)
tc59lm836dkb
Manufacturer Part Number
tc59lm836dkb
Description
288mbits Network Fcram2 ? 2,097,152-words ? 4 Banks ? 36-bits
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TC59LM836DKB.pdf
(65 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
tc59lm836dkb30B
Manufacturer:
TOSHIBA
Quantity:
189
TENTATIVE
288Mbits Network FCRAM2
− 2,097,152-WORDS × 4 BANKS × 36-BITS
DESCRIPTION
FCRAM
bits. TC59LM836DKB feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM836DKB can operate fast core cycle compared with regular DDR SDRAM.
consumption are required. The Output Driver for Network FCRAM
under light loading condition.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Network FCRAM
TC59LM836DKB is suitable for Network and other applications where large memory density and low power
t
t
t
I
l
l
•
•
Fast clock cycle time of 3.33 ns minimum
Quad Independent Banks operation
Fast cycle and Short Latency
Selectable Data Strobe
Distributed Auto-Refresh cycle in 3.9 µs
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
Organization: 2,097,152 words × 4 banks × 36 bits
Power Supply Voltage
Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL.
JTAG boundary scan
Package: 144Ball BGA, 1mm × 0.8mm Ball pitch (P-TFBGA144-1119-0.80BZ)
Notice: FCRAM is trademark of Fujitsu limited, Japan.
DD2P
DD6
CK
RC
RAC
DD1S
Fully Synchronous Operation
Double Data Rate (DDR)
Data input/output are synchronized with both edges of DS / QS.
Differential Clock (CLK and CLK ) inputs
Output data (DQs and QS) is aligned to the crossings of CLK and CLK .
Clock:
Data:
Burst Length = 2, 4
CS , FN and all address input signals are sampled on the positive edge of CLK.
CAS Latency = 4, 5, 6
TM
Clock Cycle Time (min)
Random Read/Write Cycle Time (min)
Random Access Time (max)
Operating Current (single bank) (max)
Power Down Current (max)
Self-Refresh Current (max)
containing 301,989,888 memory cells. TC59LM836DKB is organized as 2,097,152-words × 4 banks × 36
300 MHz maximum
600 Mbps/pin maximum
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TM
PARAMETER
is Double Data Rate Fast Cycle Random Access Memory. TC59LM836DKB is Network
V
V
DD
DDQ
:
: 1.4 V ~ 1.9 V
2.5 V ± 0.125V
CL = 4
CL = 5
CL = 6
360 mA
3.75 ns
3.33 ns
22.5 ns
22.5 ns
95 mA
15 mA
4.5 ns
-33
TC59LM836DKB
TM
is capable of high quality fast data transfer
340 mA
90 mA
15 mA
5.0 ns
4.5 ns
4.0 ns
25 ns
25 ns
-40
TC59LM836DKB-33,-40
2005-11-08 1/65
Rev 1.4