tc59lm913amg TOSHIBA Semiconductor CORPORATION, tc59lm913amg Datasheet - Page 11

• Manufacturer Part Number: tc59lm913amg
• Description: 512mbits Network Fcram1 Sstl_2 Interface ? 4,194,304-words ? 8 Banks ? 16-bits
• Manufacturer: TOSHIBA Semiconductor CORPORATION

L/UDQS
Command
Address
V
V
POWER UP SEQUENCE
NOTES:
CLK
CLK
V
DDQ
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
DQ
REF
PD
DD
(1)
(2)
As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
Apply V
Apply V
Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
After stable power and clock, apply DESL and take PD =H.
Issue EMRS to enable DLL and to define driver strength. (Note: 1)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
Issue two or more Auto-Refresh commands (Note: 1).
Ready for normal operation after 200 clocks from Extended Mode Register programming.
Sequence 6, 7 and 8 can be issued in random order.
L = Logic Low, H = Logic High
200us(min)
DD
DDQ
before or at the same time as V
before or at the same time as V
t
PDEX
Hi-Z
DESL
1.25V(TYP)
2.5V(TYP)
2.5V(TYP)
RDA MRS DESL
l
PDA
EMRS
op-code
EMRS
l
RSC
DDQ
REF
RDA MRS
.
.
MRS
op-code
MRS
l
RSC
DESL WRA REF
200clock cycle(min)
DESL
l
REFC
Auto Refresh cycle
TC59LM913AMG-50
WRA REF
2005-11-08 11/46
DESL
l
REFC
Normal Operation
Rev 1.1