tc59lm818dmgi-37 TOSHIBA Semiconductor CORPORATION, tc59lm818dmgi-37 Datasheet - Page 51

• Manufacturer Part Number: tc59lm818dmgi-37
• Description: 288mbits Network Fcram2 I-version
• Manufacturer: TOSHIBA Semiconductor CORPORATION

•
Addressing sequence of Sequential mode (A3)
•
(R-3) CAS Latency field (A6 to A4)
(R-4) Test Mode field (A7)
(R-5) Reserved field in the Regular Mode Register
address input to the device.
A column access is started from the inputted lower address and is performed by incrementing the lower
Addressing sequence of Interleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits
in the sequence shown as the following.
CAS Latency = 4 (Free Running QS mode)
Command
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA
command to the first data read. The minimum value of CAS Latency depends on the frequency of CLK.
In a write mode, the place of clock that should input write data is CAS Latency cycles − 1.
This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.
•
CLK
CLK
DQ
QS
Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to “0” for normal operation.
Data 0
Data 1
Data 2
Data 3
DATA
Data 0
Data 1
Data 2
Data 3
DATA
RDA
A6
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
ּּּA8 A7 A6 A5 A4 A3 A2 A1
ּּּA8 A7 A6 A5 A4 A3 A2
ּּּA8 A7 A6 A5 A4 A3 A2
0
0
0
0
1
1
1
1
ACCESS ADDRESS
Addressing sequence for Sequential mode
Addressing sequence for Interleave mode
LAL
n + 1
n + 2
n + 3
A5
N
0
0
1
1
0
0
1
1
ACCESS ADDRESS
A4
0
1
0
1
0
1
0
1
2 words (address bits is LA0)
not carried from LA0~LA1
4 words (address bits is LA1, LA0)
not carried from LA1~LA2
A
A
1
1
BURST LENGTH
CAS LATENCY
A
A0
A
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
4
5
6
BURST LENGTH
2 words
4 words
TC59LM818DMGI-37
Data
0
2005-11-08 51/55
Data
1
Data
2
Data
Rev 1.2
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