ICS2008 Integrated Circuit System, ICS2008 Datasheet - Page 15

• Manufacturer Part Number: ICS2008
• Description: Smptetime Code Receiver / Generator
• Manufacturer: Integrated Circuit System

Applications
Crystal Oscillator
This oscillator will operate
properly with either a serial or
parallel resonant crystal. If fre-
quency accuracy is critical,
a parallel resonant crystal is
recommended.
Threshold Bypass Pins
These pins provide access to the internal references for clamp
level (CTHRESH), SYNC slicer (STHRESH), and data slicer
(DTHRESH). In general, these pins are left open, and the
levels are output. However, should the user want to set other
levels, these pins can be over-driven with the desired
threshold level(s).
0.14V above CTHRESH. The SYNC separator ignores short
pulses which fall below the STHRESH level such as these that
come from the chroma component of the video. DTHRESH is
the data slicer reference. It is nominally 0.57V above
CTHRESH.
Video Inputs
Y1, Y2, C1 and C2 pins
must be capacitively
coupled to the terminated
video source(s). These
inputs are clamped to the
CTHRESH level. A typi-
cal coupling capacitance
is 0.1 F.
Fig. 5 – Threshold Bias
Fig. 4 - Crystal Oscillator
Fig. 6 – S-Video Input
CTHRESH is the thresh-
old to which the input
video
clamped. The CTHRESH
level is nominally 1.3V.
With the incoming video
riding on this 1.3V DC
level, the internal SYNC
separator sizes the video
at 20 IRE up from the
SYNC tips. This level,
STHRESH, is nominally
sync
tips
are
15
Video Outputs
YOUT and COUT are
outputs of analog multi-
plexers which select the
video source from Y1,
C1 or Y2, C2. These
outputs are not buffered,
so minimizes signal dis-
tortion. It is, therefore,
important to keep the
capacitive and resistive
load on the YOUT and
COUT pins to a mini-
mum. If DC coupling is desired, the plus input of the opamp
should be high impedance with a low bias current, and its out-
put should be able to drive a 75 ohm load with an appropriate
video bandwidth. In general, composite NTSC and S-video
signals have a bandwidth of 4.2 MHz. A minimum output
buffer bandwidth of 10 MHz is recommended. Care should
be taken in board layout to minimize stray capacitance on
the YOUT and COUT pins. Otherwise, there could be high
frequency roll-off which could result in a loss of chrominance
amplitude.
Self Biased Inputs
The CLICK and FRAME inputs are biased to 1/2 VDD and
connected to plus inputs of two comparators. The minus
inputs are internally biased to 1/2 VDD. When CLICK
or FRAME sources are
analog, they should be ca-
pacitively coupled to the
input pin. However, if the
sources are digital, they
may be tied to the pins
directly. It is important to
make sure that the digital
levels into these pins
swing above and below the
1/2 VDD threshold of the
comparators. This is not
a problem with digital
CMOS sources, but it could
be with TTL sources.
LTCIN + and LTCIN – are
comparator inputs for the
LTC input. This differential
input is provided to maximize noise immunity. If the LTC
source is single ended, the LTCIN – should be capacitively
coupled to the ground reference of that source. If the LTC
source is digital, set the LTCIN – to the desired threshold, and
connect the digital source to LTCIN+.
Fig. 8 - Self Biased Inputs
Fig. 7 - Video Output
ICS2008B
ICS2008B Rev B 6/6/01