lp3856et-adj National Semiconductor Corporation, lp3856et-adj Datasheet - Page 12

• Manufacturer Part Number: lp3856et-adj
• Description: 3a Fast Response Ultra Low Dropout Linear Regulators
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Hints
input, output, and ground pins of the LP3856-ADJ using
traces which do not have other currents flowing in them
(Kelvin connect).
The best way to do this is to lay out C
device with short traces to the V
The regulator ground pin should be connected to the exter-
nal circuit ground so that the regulator and its capacitors
have a "single point ground".
It should be noted that stability problems have been seen in
applications where "vias" to an internal ground plane were
used at the ground points of the IC and the input and output
capacitors. This was caused by varying ground potentials at
these nodes resulting from current flowing through the
ground plane. Using a single point ground technique for the
regulator and it’s capacitors fixed the problem.
Since high current flows through the traces going into V
and coming from V
these pins so there is no voltage drop in series with the input
and output capacitors.
RFI/EMI SUSCEPTIBILITY
RFI (radio frequency interference) and EMI (electromagnetic
interference) can degrade any integrated circuit’s perfor-
mance because of the small dimensions of the geometries
inside the device. In applications where circuit sources are
present which generate signals with significant high fre-
quency energy content (
ensure that this does not affect the IC regulator.
If RFI/EMI noise is present on the input side of the regulator
(such as applications where the input source comes from the
output of a switching regulator), good ceramic bypass ca-
pacitors must be used at the input pin of the IC.
If a load is connected to the IC output which switches at high
speed (such as a clock), the high-frequency current pulses
required by the load must be supplied by the capacitors on
the IC output. Since the bandwidth of the regulator loop is
less than 100 kHz, the control circuitry cannot respond to
load changes above that frequency. The means the effective
output impedance of the IC at frequencies above 100 kHz is
determined only by the output capacitor(s).
In applications where the load is switching at high speed, the
output of the IC may need RF isolation from the load. It is
recommended that some inductance be placed between the
output capacitor and the load, and good RF bypass capaci-
tors be placed directly across the load.
PCB layout is also critical in high noise environments, since
RFI/EMI is easily radiated directly into PC traces. Noisy
circuitry should be isolated from "clean" circuits where pos-
sible, and grounded through a separate path. At MHz fre-
quencies, ground planes begin to look inductive and RFI/
EMI can cause ground bounce across the ground plane.
In multi-layer PCB applications, care should be taken in
layout so that noisy power and ground planes do not radiate
directly into adjacent layers which carry analog power and
ground.
OUTPUT NOISE
Noise is specified in two ways-
Spot Noise or Output noise density is the RMS sum of all
noise sources, measured at the regulator output, at a spe-
cific frequency (measured with a 1Hz bandwidth). This type
of noise is usually plotted on a curve as a function of fre-
quency.
OUT
, Kelvin connect the capacitor leads to
>
1 MHz), care must be taken to
(Continued)
IN
, V
OUT
IN
and C
, and ground pins.
OUT
near the
IN
12
Total output Noise or Broad-band noise is the RMS sum
of spot noise over a specified bandwidth, usually several
decades of frequencies.
Attention should be paid to the units of measurement. Spot
noise is measured in units µV/
noise is measured in µV(rms).
The primary source of noise in low-dropout regulators is the
internal reference. In CMOS regulators, noise has a low
frequency component and a high frequency component,
which depend strongly on the silicon area and quiescent
current. Noise can be reduced in two ways: by increasing the
transistor area or by increasing the current drawn by the
internal reference. Increasing the area will decrease the
chance of fitting the die into a smaller package. Increasing
the current drawn by the internal reference increases the
total supply current (ground pin current). Using an optimized
trade-off of ground pin current and die size, LP3856-ADJ
achieves low noise performance and low quiescent current
operation.
The total output noise specification for LP3856-ADJ is pre-
sented in the Electrical Characteristics table. The Output
noise density at different frequencies is represented by a
curve under typical performance characteristics.
SHORT-CIRCUIT PROTECTION
The LP3856-ADJ is short circuit protected and in the event of
a peak over-current condition, the short-circuit control loop
will rapidly drive the output PMOS pass element off. Once
the power pass element shuts down, the control loop will
rapidly cycle the output on and off until the average power
dissipation causes the thermal shutdown circuit to respond
to servo the on/off cycling to a lower frequency. Please refer
to the section on thermal information for power dissipation
calculations.
SHUTDOWN OPERATION
A CMOS Logic level signal at the shutdown ( SD) pin will
turn-off the regulator. Pin SD must be actively terminated
through a 10kΩ pull-up resistor for a proper operation. If this
pin is driven from a source that actively pulls high and low
(such as a CMOS rail to rail comparator), the pull-up resistor
is not required. This pin must be tied to Vin if not used.
DROPOUT VOLTAGE
The dropout voltage of a regulator is defined as the minimum
input-to-output differential required to stay within 2% of the
nominal output voltage. For CMOS LDOs, the dropout volt-
age is the product of the load current and the Rds(on) of the
internal MOSFET.
REVERSE CURRENT PATH
The internal MOSFET in LP3856-ADJ has an inherent para-
sitic diode. During normal operation, the input voltage is
higher than the output voltage and the parasitic diode is
reverse biased. However, if the output is pulled above the
input in an application, then current flows from the output to
the input as the parasitic diode gets forward biased. The
output can be pulled above the input as long as the current
in the parasitic diode is limited to 200mA continuous and 1A
peak.
POWER DISSIPATION/HEATSINKING
The LP3856-ADJ can deliver a continuous current of 3A over
the full operating temperature range. A heatsink may be
required depending on the maximum power dissipation and
maximum ambient temperature of the application. Under all
√
Hz or nV/
√
Hz and total output