x45620 Intersil Corporation, x45620 Datasheet - Page 10

• Manufacturer Part Number: x45620
• Description: Dual Voltage Monitor With Integrated System Battery Switch And Eeprom
• Manufacturer: Intersil Corporation

WDO Output Timing
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X45620 activates a Power-
on Reset Circuit. This circuit goes active at about 1V
and pulls the RESET pin active. This signal prevents
the system microprocessor from starting to operate
with insufficient voltage or prior to stabilization of the
oscillator. When Vcc exceeds the device V
for t
processor to begin executing code.
Low V
During operation, the X45620 monitors the V
and asserts RESET if supply voltage falls below a pre-
set minimum V
tion to the device is interrupted. The RESET signal also
prevents the microprocessor from operating in a power
fail or brownout condition. The RESET signal remains
active until the voltage drops below 1V. RESET also
remains active until V
for t
Low V2MON Voltage Monitoring
The X45620 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V
Figure 1. Two Uses of Dual Voltage Monitoring
Symbol
PURST
Unregulated
PURST
t
t
WDO
RST
CC
Supply
TRIP2
(V1MON) Voltage Monitoring
.
R1 and R2 selected so V2 = V2MON threshold when
Unregulated supply reaches 6V.
R1
R2
the circuit releases RESET, allowing the
. The V2FAIL signal is either ORed with
TRIP1
Watchdog Time Out Period,
Reset Time Out
Reg
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
5V
. During this time the communica-
CC
returns and exceeds V
10
V
V2MON
Parameter
CC
X45620
V2FAIL
RESET
V
OUT
TRIP1
CC
value
TRIP1
System
Reset
System
Interrupt
level
X45620
Min
200
500
75
75
Unregulated
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until V2MON returns and exceeds V
The V2MON circuit is powered by V
both V
not be monitored.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring SDA and SCL pin. In normal
operation, the microprocessor must periodically restart
the Watchdog Timer to prevent WDO from going
active. The watchdog timer is restarted on the first
HIGH to LOW transition on SCL after a start com-
mand. The start command is defined as SDA going
HIGH to LOW while SCL is HIGH. The state of two
nonvolatile control bits in the Status Register deter-
mines the watchdog timer period. The microprocessor
can change these watchdog bits by writing to the sta-
tus register. The factory default setting disables the
watchdog timer.
The Watchdog Timer oscillator stops and resets when
in battery backup mode. It re-starts when V
Supply
Typ (6)
150
400
800
150
Notice: No external components required to monitor
two voltages.
CC
and V
Reg
5V
3.0V
Reg
1200
Max
250
600
250
BATT
are at or below Vtrip, V2MON will
V
V2MON
CC
Unit
ms
ms
ms
ms
X45620
RESET
V2FAIL
Test Conditions
TRIP2
CC
Note 4
Note 4
.
V
(or V
System
Reset
OUT
CC
returns.
July 29, 2005
BATT
FN8250.0
). If